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Clarify authorisation of PREFETCH.I in integer mode #900

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Clarify authorisation of PREFETCH.I in integer mode #900

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ac60d92
remove out of date PCC refernce
tariqkurd-repo Dec 16, 2025
a49a207
Merge branch 'main' into remove_pcc_reference
tariqkurd-repo Dec 18, 2025
fdbed73
change to a recommendation
tariqkurd-repo Dec 24, 2025
98f8811
Update src/cheri/riscv-hybrid-integration.adoc
tariqkurd-repo Jan 30, 2026
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6 changes: 4 additions & 2 deletions src/cheri/riscv-hybrid-integration.adoc
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Expand Up @@ -34,8 +34,10 @@ NOTE: Instructions which are _modified_ on an {cheri_base_ext_name} architecture
All <<rvy_insn_table>> instructions, and associated CSRs, are available in addition to RVI/RVE and all supported non-CHERI extensions.
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The authorizing capability for memory access is <<ddc>> (as opposed to `rs1`).
That is, all memory accesses, including <<PREFETCH_W_CHERI>> and <<PREFETCH_R_CHERI>>, are implicitly authorized by <<ddc>> and only the memory address is sourced from `rs1`.
<<PREFETCH_I_CHERI>> is the exception to this rule, as <<pcc>> authorizes it.
That is, all memory accesses, including <<PREFETCH_W_CHERI>>, <<PREFETCH_R_CHERI>> are implicitly authorized by <<ddc>> and only the memory address is sourced from `rs1`.
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NOTE: It is recommended to authorize the prefetched address of <<PREFETCH_I_CHERI>> against <<pcc>> instead of <<ddc>>.
High performance implementations may not have access to the <<pcc>> available to perform this check, as <<pcc>> bounds are not otherwise required in the load/store unit.
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NOTE: <<ddc>> is also used to authorize {cheri_base_ext_name} specific memory instructions such as <<LOAD_CAP>> and <<STORE_CAP>>.
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