Clarify scope of {dmcontrol.ndmreset} when multiple Debug Modules exist in one SoC

[xiaoweish]

The Debug Spec states that
{dmcontrol-ndmreset} resets all the harts in the hardware platform, as well as all other parts of the hardware platform except for the Debug Modules, Debug Transport Modules, and Debug Module Interface.
Link here:

riscv-debug-spec/debug_module.adoc

Lines 69 to 72 in 22a7576

	There are two methods that allow a debugger to reset harts. {dmcontrol-ndmreset} resets all
	the harts in the hardware platform, as well as all other parts of the
	hardware platform except for the Debug Modules, Debug Transport Modules,
	and Debug Module Interface. Exactly what is affected by this reset is

In SoCs that integrate multiple RISC-V CPU clusters, each with its own Debug Module and Debug Transport Module (e.g., two separate JTAG debug chains for CPU-A and CPU-B), the term “hardware platform” becomes ambiguous.

For example:

CPU-A has its own DM/DTM connected via JTAG chain A.

CPU-B has its own DM/DTM connected via JTAG chain B.

If a debugger issues ndmreset through CPU-A’s DTM, should this reset also affect CPU-B’s harts and debug module?
Or is ndmreset only expected to reset the harts visible to the DM receiving the command (i.e., within that DM’s reset domain)?

It would be helpful if the spec explicitly clarified whether ndmreset is scoped per Debug Module instance, or if any global system-wide coordination is expected.

[pdonahue-ventana]

The spec says:

ndmreset resets all the harts in the hardware platform, as well as all other parts of the hardware platform except for the Debug Modules, Debug Transport Modules, and Debug Module Interface. Exactly what is affected by this reset is implementation dependent, but it must be possible to debug programs from the first instruction executed.

It's implementation dependent whether something like the interconnect is reset, though it does require "all the harts in the hardware platform" to be reset. The term "hardware platform" is defined in section 1.1:

A single system consisting of one or more components.

And "component" is:

A RISC-V core, or other part of a hardware platform. Typically all components will be connected to a single system bus.

That's a circular definition where a hardware platform is a group of components and a component is a part of a hardware platform. That's not helpful. I never noticed this circularity before.

I'm not sure if there's a basis for this in the spec but I intuitively thought that ndmreset controlled at a minimum all of the harts connected to this DM and that there is no maximum (except that the DM, DTM, and DMI cannot be reset). In my mind, it all depends on implementation choices about reset domains. It would be nice to have the spec provide better guidance and avoid circular definitions.