Update v-st-ext.adoc

More concise, "vector register (or a vector register group)" => "vector register group"

Signed-off-by: DmitryUtyansky <118922093+DmitryUtyansky@users.noreply.github.com>

Author: DmitryUtyansky

src/v-st-ext.adoc

@@ -3930,9 +3930,9 @@ destination format is converted to the destination format's largest finite value
 === Vector Reduction Operations
 
 [#norm:vreduction_scalar_def]#Vector reduction operations take a vector register group of elements
-and a scalar held in element 0 of a vector register (or a vector register group), and perform a
+and a scalar held in element 0 of a vector register group, and perform a
 reduction using some binary operator, to produce a scalar result in
-element 0 of a vector register (or a vector register group).#  [#norm:vreduction_scalar_disregard_LMUL]#The scalar input and output operands
+element 0 of a vector register group.#  [#norm:vreduction_scalar_disregard_LMUL]#The scalar input and output operands
 are held in element 0 of a group with EMUL=ceil(EEW/VLEN) regardless of LMUL setting.#
 
 NOTE: The previous edition specified use of a single vector register (EMUL=1). EMUL = ceil(EEW/VLEN) allows for a case