Update v-st-ext.adoc

Minor rewording of mapping for LMUL > 1

Signed-off-by: DmitryUtyansky <118922093+DmitryUtyansky@users.noreply.github.com>

Author: DmitryUtyansky

src/v-st-ext.adoc

@@ -783,10 +783,10 @@ next-highest-numbered vector register in the group once each vector
 register is filled.
 
 If a vector extension supports EEW > VLEN, one element can span multiple
-vector registers and to have EEW bits to hold one element the requirement is that
-the LMUL {ge} EEW/VLEN. In this case
-each element occupies multiple consecutive vector registers, the least
-significant bits of each element go to the lower-numbered vector register.
+vector registers, in which case the least-significant bits of the element
+are held in the lowest-numbered vector register.
+Instructions that access vector register groups with EMUL < EEW/VLEN are
+reserved.
 
 ----
  LMUL > 1 examples