Update v-st-ext.adoc

Misc. small syntax corrections & rephrasing according to the feedbacks.

Signed-off-by: DmitryUtyansky <118922093+DmitryUtyansky@users.noreply.github.com>

Author: DmitryUtyansky

src/v-st-ext.adoc

@@ -21,15 +21,15 @@ Each hart supporting a vector extension defines two parameters:
 
 . [#norm:elen]#The maximum size in bits of a vector element that any operation can produce or consume, _ELEN_ {ge} 8, which
 must be a power of 2.#
-. [#norm:vlen]#The number of bits in a single vector register, _VLEN_, which must be a power of 2, and must be no greater than 2^16^.#
+. [#norm:vlen]#The number of bits in a single vector register, _VLEN_ {ge} 8, which must be a power of 2, and must be no greater than 2^16^.#
 
 Standard vector extensions (<<sec-vector-extensions>>) and
 architecture profiles may set further constraints on _ELEN_ and _VLEN_.
 
-NOTE: Future extensions may allow ELEN {gt} VLEN by holding one
+NOTE: Future extensions may allow ELEN > VLEN by holding one
 element using bits from multiple vector registers. The formulas in this
 specification have been updated to allow this. The changes only
-affect ELEN {gt} VLEN cases, when ELEN {le} VLEN nothing is changed.
+affect ELEN > VLEN cases, when ELEN {le} VLEN nothing is changed.
 E.g.: EMUL for "scalar in vector" inputs/outputs of reductions is now
 defined as ceil(EEW/VLEN), so it is still 1 (specifying a single register,
 as before) when EEW {le} VLEN. Element width for whole vector register
@@ -288,8 +288,7 @@ register-resident vectors.
 Implementations must provide fractional LMUL settings that allow the
 narrowest supported type to occupy a fraction of a vector register
 corresponding to the ratio of the narrowest supported type's width to
-that of the largest supported type's width or to the vector register length,
-if the latter is smaller than the largest supported type (ELEN/VLEN > 1).
+the smaller of VLEN and the largest supported type's width.
 In general, the requirement is to support LMUL {ge} SEW~MIN~/min(ELEN, VLEN),
 where SEW~MIN~ is the narrowest supported SEW value, ELEN is the widest
 supported SEW value and VLEN is the number of bits in a vector register.
@@ -1060,7 +1059,7 @@ Widened scalar values, e.g., input and output to a widening reduction
 operation, are held in the first element of a vector register and
 have EMUL=1.
 If a vector extension supports EEW/VLEN > 1, EEW-wide widened scalar
-values are held in a vector register group with EMUL = EEW/VLEN
+values are held in a vector register group with EMUL = EEW/VLEN.
 
 ==== Vector Masking
 
@@ -2109,11 +2108,11 @@ The full set of EEW variants is provided so that the encoded EEW can be used
 as a hint to indicate the destination register group will next be accessed
 with this EEW, which aids implementations that rearrange data internally.
 
-In vector extensions supporting ELEN/VLEN {gt} 1, element size can exceed
+In vector extensions supporting ELEN/VLEN > 1, element size can exceed
 the number of bits available in a vector register or a vector register
-group. In that case whole vector register load instructions
+group. In that case, the whole vector register load instructions
 still operate on the specified number of vector register(s), using the
-least significant bits of the element.
+least-significant bits of the element.
 
 The vector whole register store instructions are encoded similar to
 unmasked unit-stride store of elements with EEW=8.
@@ -3936,7 +3935,7 @@ destination format is converted to the destination format's largest finite value
 and a scalar held in element 0 of a vector register group, and perform a
 reduction using some binary operator, to produce a scalar result in
 element 0 of a vector register group.#  [#norm:vreduction_scalar_disregard_LMUL]#The scalar input and output operands
-are held in element 0 of a group with EMUL=ceil(EEW/VLEN) regardless of LMUL setting.#
+are held in element 0 of a group with EMUL=ceil(EEW/VLEN), regardless of LMUL setting.#
 
 [#norm:vreduction_vd_overlap_vs]#The destination vector register can overlap the source operands,
 including the mask register.#
@@ -4566,7 +4565,7 @@ and `vmv.s.x` are reserved.#
 
 The floating-point scalar read/write instructions transfer a single
 value between a scalar `f` register and element 0 of a vector
-register group with EMUL=ceil(EEW/VLEN).  [#norm:vfmv-f-s_vfmv-s-f_ignoreLMUL]##The instructions ignore LMUL, EMUL is computed as ceil(EEW/VLEN).#
+register group with EMUL=ceil(EEW/VLEN).  [#norm:vfmv-f-s_vfmv-s-f_ignoreLMUL]##The instructions ignore LMUL; EMUL is computed as ceil(EEW/VLEN).#
 
 ----
 vfmv.f.s rd, vs2  # f[rd] = vs2[0] (rs1=0)
@@ -4909,7 +4908,7 @@ e q r d c b v a    # v11 destination after vrgather using viota.m under mask
 [#norm:vmv-nr-r_op]#The `vmv<nr>r.v` instructions copy whole vector registers (i.e., all
 VLEN bits) and can copy whole vector register groups.  The `nr` value
 in the opcode is the number of individual vector registers, NREG, to
-copy.  The instructions operate as if EEW=min(VLEN, SEW), EMUL = NREG, effective
+copy.  The instructions operate as if EEW=min(VLEN, SEW), EMUL = NREG, and effective
 length `evl`= EMUL * VLEN/EEW.#
 
 NOTE: These instructions are intended to aid compilers to shuffle