I'm porting UDB to describe a full RISC-V SoC, not just the ISA. A large part of any SoC's programmer-visible interface lives in memory-mapped register space (CLINT/ACLINT, PLIC, custom device registers), not CSR space. UDB already has first-class support for CSRs with schemas, field definitions, WaveDrom diagrams, and PDF rendering -- but nothing equivalent for memory-mapped registers. This forces SoC-level documentation to be maintained outside the database.

My SoC has ~40 memory-mapped registers (IPI triggers, flow-control credits, barrier synchronization) that have physical addresses, bit-field layouts, reset values, and belong to defining extensions -- structurally identical to CSRs, just addressed differently. I want these rendered in the generated PDF alongside CSRs and instructions, with the same field diagrams and descriptions.

The idea would be to add an mmr object kind alongside csr and inst: a schema similar to csr_schema.json but with physical_address instead of 12-bit CSR address and without CSR-specific fields like priv_mode, YAML spec files under spec/{std,custom}/isa/<group>/mmr/<Extension>/, a Ruby model reusing CsrField for field definitions, and PDF backend support for rendering MMR sections with address tables and field diagrams.

I have a working prototype on my fork. Happy to open a PR if there's interest.