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Add Zilsd/Zclsd Support
Co-authored-by: Simona Costinescu <simona.costinescu@nxp.com>
1 parent efdfe9b commit 248f935

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‎README.md‎

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@@ -137,6 +137,7 @@ For booting operating system images, see the information under the
137137
- Zic64b extension for Cache block size is 64 bytes, v1.0
138138
- Zicbom, Zicbop and Zicboz extensions for cache-block management, v1.0
139139
- Zicfilp extension for Landing Pad Control Flow Integrity, v1.0
140+
- Zilsd and Zclsd extensions for RV32 Load/Store pair instructions, v1.0
140141
- Zimop extension for May-Be-Operations, v1.0
141142
- Zihintntl extension for Non-temporal Locality Hints, v1.0
142143
- Zihintpause extension for Pause Hint, v2.0

‎build_simulator.sh‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22

33
set -e
44
: "${DOWNLOAD_GMP:=TRUE}"
5-
: "${ENABLE_RISCV_TESTS:=TRUE}"
6-
cmake -S . -B build -DCMAKE_BUILD_TYPE=RelWithDebInfo -DDOWNLOAD_GMP="${DOWNLOAD_GMP}" -DENABLE_RISCV_TESTS="${ENABLE_RISCV_TESTS}"
5+
: "${ENABLE_RISCV_TESTS:=FALSE}"
6+
cmake -S . -B build -DCMAKE_BUILD_TYPE=RelWithDebInfo -DDOWNLOAD_GMP="${DOWNLOAD_GMP}" -DENABLE_RISCV_TESTS="${ENABLE_RISCV_TESTS}" -DFIRST_PARTY_TESTS=TRUE
77
jobs=$( (nproc || sysctl -n hw.ncpu || echo 2) 2>/dev/null)
88
cmake --build build -j${jobs}

‎config/config.json.in‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,11 @@
6666
// The configuration option determines how to handle the reserved behavior: Odd-numbered registers for RV32Zdinx.
6767
// "Zdinx_Fatal" – raise a Sail exception, stopping execution.
6868
// "Zdinx_Illegal" – treat it as an illegal instruction.
69-
"rv32zdinx_odd_register": "Zdinx_Illegal"
69+
"rv32zdinx_odd_register": "Zdinx_Illegal",
70+
// The configuration option determines how to handle the reserved behavior: Odd-numbered registers for Zilsd and Zclsd.
71+
// "LoadStorePair_Fatal" – raise a Sail exception, stopping execution.
72+
// "LoadStorePair_Illegal" – treat it as an illegal instruction.
73+
"rv32load_store_pair_odd_register": "LoadStorePair_Illegal"
7074
}
7175
},
7276
"memory": {
@@ -276,6 +280,9 @@
276280
"Zihpm": {
277281
"supported": true
278282
},
283+
"Zilsd": {
284+
"supported": @CONFIG_XLEN_IS_32@
285+
},
279286
"Zimop": {
280287
"supported": true
281288
},
@@ -333,6 +340,9 @@
333340
"Zcb": {
334341
"supported": true
335342
},
343+
"Zclsd": {
344+
"supported": false
345+
},
336346
"Zcmop": {
337347
"supported": true
338348
},

‎model/core/extensions.sail‎

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Original file line numberDiff line numberDiff line change
@@ -122,6 +122,10 @@ function clause hartSupports(Ext_Zihintpause) = config extensions.Zihintpause.su
122122
enum clause extension = Ext_Zihpm
123123
mapping clause extensionName = Ext_Zihpm <-> "zihpm"
124124
function clause hartSupports(Ext_Zihpm) = config extensions.Zihpm.supported
125+
// Load/Store Pair for RV32
126+
enum clause extension = Ext_Zilsd
127+
mapping clause extensionName = Ext_Zilsd <-> "zilsd"
128+
function clause hartSupports(Ext_Zilsd) = config extensions.Zilsd.supported : bool & (xlen == 32)
125129
// May-Be-Operations
126130
enum clause extension = Ext_Zimop
127131
mapping clause extensionName = Ext_Zimop <-> "zimop"
@@ -244,6 +248,11 @@ enum clause extension = Ext_Zbs
244248
mapping clause extensionName = Ext_Zbs <-> "zbs"
245249
function clause hartSupports(Ext_Zbs) = config extensions.Zbs.supported
246250

251+
// Compressed Load/Store pair instructions
252+
enum clause extension = Ext_Zclsd
253+
mapping clause extensionName = Ext_Zclsd <-> "zclsd"
254+
function clause hartSupports(Ext_Zclsd) = config extensions.Zclsd.supported : bool & (xlen == 32)
255+
247256
// Scalar & Entropy Source Instructions: NIST Suite: AES Decryption
248257
enum clause extension = Ext_Zknd
249258
mapping clause extensionName = Ext_Zknd <-> "zknd"
@@ -611,6 +620,7 @@ let extensions_ordered_for_isa_string = [
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Ext_Zicntr,
612621
Ext_Zicond,
613622
Ext_Zicsr,
623+
Ext_Zilsd,
614624
Ext_Zifencei,
615625
Ext_Zihintntl,
616626
Ext_Zihintpause,
@@ -644,6 +654,7 @@ let extensions_ordered_for_isa_string = [
644654
Ext_Zcb,
645655
Ext_Zcd,
646656
Ext_Zcf,
657+
Ext_Zclsd,
647658
Ext_Zcmop,
648659

649660
// Zb

‎model/core/platform_config.sail‎

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Original file line numberDiff line numberDiff line change
@@ -91,9 +91,15 @@ enum RV32ZdinxOddRegisterReservedBehavior = {
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Zdinx_Illegal,
9292
}
9393

94+
enum RV32LoadStorePairOddRegisterReservedBehavior = {
95+
LoadStorePair_Fatal,
96+
LoadStorePair_Illegal,
97+
}
98+
9499
let amocas_odd_register_reserved_behavior : AmocasOddRegisterReservedBehavior = config base.reserved_behavior.amocas_odd_register
95100
let fcsr_rm_reserved_behavior : FcsrRmReservedBehavior = config base.reserved_behavior.fcsr_rm
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let pmp_write_only_reserved_behavior : PmpWriteOnlyReservedBehavior = config base.reserved_behavior.pmpcfg_write_only
97102
let xenvcfg_cbie_reserved_behavior : XenvcfgCbieReservedBehavior = config base.reserved_behavior.xenvcfg_cbie
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let xtvec_mode_reserved_behavior : XtvecModeReservedBehavior = config base.reserved_behavior.xtvec_mode
99104
let rv32zdinx_odd_register_reserved_behavior : RV32ZdinxOddRegisterReservedBehavior = config base.reserved_behavior.rv32zdinx_odd_register
105+
let rv32load_store_pair_odd_register_reserved_behavior : RV32LoadStorePairOddRegisterReservedBehavior = config base.reserved_behavior.rv32load_store_pair_odd_register

‎model/extensions/FD/zcf_insts.sail‎

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Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
// SPDX-License-Identifier: BSD-2-Clause
77
// =======================================================================================
88

9-
function clause currentlyEnabled(Ext_Zcf) = hartSupports(Ext_Zcf) & currentlyEnabled(Ext_F) & currentlyEnabled(Ext_Zca) & (currentlyEnabled(Ext_C) | not(hartSupports(Ext_C)))
9+
function clause currentlyEnabled(Ext_Zcf) = hartSupports(Ext_Zcf) & currentlyEnabled(Ext_F) & currentlyEnabled(Ext_Zca) & (currentlyEnabled(Ext_C) | not(hartSupports(Ext_C))) & not(currentlyEnabled(Ext_Zclsd))
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1111
union clause instruction = C_FLWSP : (bits(6), fregidx)
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‎model/extensions/Zclsd/zclsd_insts.sail‎

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@@ -0,0 +1,92 @@
1+
/*=======================================================================================*/
2+
/* This Sail RISC-V architecture model, comprising all files and */
3+
/* directories except where otherwise noted is subject the BSD */
4+
/* two-clause license in the LICENSE file. */
5+
/* */
6+
/* SPDX-License-Identifier: BSD-2-Clause */
7+
/*=======================================================================================*/
8+
9+
function clause currentlyEnabled(Ext_Zclsd) = hartSupports(Ext_Zilsd) & currentlyEnabled(Ext_Zca) & not(currentlyEnabled(Ext_Zcf)) & xlen == 32
10+
11+
// RV32Zclsd requires even register pairs
12+
function validZclsdReg(reg : regidx) -> bool = {
13+
if encdec_reg(reg)[0] == 0b1
14+
then match rv32load_store_pair_odd_register_reserved_behavior {
15+
LoadStorePair_Fatal => reserved_behavior("Zclsd used odd-numbered register " ^ dec_str(unsigned(encdec_reg(reg)))),
16+
LoadStorePair_Illegal => return false,
17+
};
18+
true
19+
}
20+
function validZclsdCReg(reg : cregidx) -> bool = {
21+
if encdec_creg(reg)[0] == 0b1
22+
then match rv32load_store_pair_odd_register_reserved_behavior {
23+
LoadStorePair_Fatal => reserved_behavior("Zclsd used odd-numbered register " ^ dec_str(unsigned(encdec_creg(reg)))),
24+
LoadStorePair_Illegal => return false,
25+
};
26+
true
27+
}
28+
29+
/* ****************************************************************** */
30+
union clause instruction = ZCLSD_C_LDSP : (bits(9), regidx)
31+
32+
$[wavedrom "C.LDSP offset[5] dest offset[4:3|8:6] C2"]
33+
mapping clause encdec_compressed = ZCLSD_C_LDSP(ui86 @ ui5 @ ui43 @ 0b000, rd)
34+
<-> 0b011 @ ui5 : bits(1) @ encdec_reg(rd) @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10
35+
when currentlyEnabled(Ext_Zclsd) & validZclsdReg(rd) & rd != zreg
36+
37+
function clause execute (ZCLSD_C_LDSP(imm, rd)) = {
38+
ExecuteAs(ZILSD_LD(zero_extend(imm), sp, rd))
39+
}
40+
41+
mapping clause assembly = ZCLSD_C_LDSP(uimm, rd)
42+
<-> "c.ldsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_9(uimm)
43+
when rd != zreg
44+
45+
/* ****************************************************************** */
46+
union clause instruction = ZCLSD_C_SDSP : (bits(9), regidx)
47+
48+
$[wavedrom "C.SDSP offset[5:3|8:6] src C2"]
49+
mapping clause encdec_compressed = ZCLSD_C_SDSP(ui86 @ ui53 @ 0b000, rs2)
50+
<-> 0b111 @ ui53 : bits(3) @ ui86 : bits(3) @ encdec_reg(rs2) @ 0b10
51+
when currentlyEnabled(Ext_Zclsd) & validZclsdReg(rs2)
52+
53+
function clause execute (ZCLSD_C_SDSP(uimm, rs2)) = {
54+
ExecuteAs(ZILSD_SD(zero_extend(uimm), rs2, sp))
55+
}
56+
57+
mapping clause assembly = ZCLSD_C_SDSP(uimm, rs2)
58+
<-> "c.sdsp" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_9(uimm)
59+
60+
/* ****************************************************************** */
61+
union clause instruction = ZCLSD_C_LD : (bits(8), cregidx, cregidx)
62+
63+
$[wavedrom "C.LD offset[5:3] base offset[7:6] dest C0"]
64+
mapping clause encdec_compressed = ZCLSD_C_LD(ui76 @ ui53 @ 0b000, rs1, rd)
65+
<-> 0b011 @ ui53 : bits(3) @ encdec_creg(rs1) @ ui76 : bits(2) @ encdec_creg(rd) @ 0b00
66+
when currentlyEnabled(Ext_Zclsd) & validZclsdCReg(rd)
67+
68+
function clause execute (ZCLSD_C_LD(uimm, rsc, rdc)) = {
69+
let rd = creg2reg_idx(rdc);
70+
let rs = creg2reg_idx(rsc);
71+
ExecuteAs(ZILSD_LD(zero_extend(uimm), rs, rd))
72+
}
73+
74+
mapping clause assembly = ZCLSD_C_LD(uimm, rsc, rdc)
75+
<-> "c.ld" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_8(uimm)
76+
77+
/* ****************************************************************** */
78+
union clause instruction = ZCLSD_C_SD : (bits(8), cregidx, cregidx)
79+
80+
$[wavedrom "C.SD offset[5:3] base offset[7:6] src C0"]
81+
mapping clause encdec_compressed = ZCLSD_C_SD(ui76 @ ui53 @ 0b000, rs1, rs2)
82+
<-> 0b111 @ ui53 : bits(3) @ encdec_creg(rs1) @ ui76 : bits(2) @ encdec_creg(rs2) @ 0b00
83+
when currentlyEnabled(Ext_Zclsd) & validZclsdCReg(rs2)
84+
85+
function clause execute (ZCLSD_C_SD(uimm, rsc1, rsc2)) = {
86+
let rs1 = creg2reg_idx(rsc1);
87+
let rs2 = creg2reg_idx(rsc2);
88+
ExecuteAs(ZILSD_SD(zero_extend(uimm), rs2, rs1))
89+
}
90+
91+
mapping clause assembly = ZCLSD_C_SD(uimm, rsc1, rsc2)
92+
<-> "c.sd" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_8(uimm)

‎model/extensions/Zilsd/zilsd_insts.sail‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
/*=======================================================================================*/
2+
/* This Sail RISC-V architecture model, comprising all files and */
3+
/* directories except where otherwise noted is subject the BSD */
4+
/* two-clause license in the LICENSE file. */
5+
/* */
6+
/* SPDX-License-Identifier: BSD-2-Clause */
7+
/*=======================================================================================*/
8+
9+
function clause currentlyEnabled(Ext_Zilsd) = hartSupports(Ext_Zilsd) & xlen == 32
10+
11+
// Zilsd requires even register pairs
12+
function validZilsdReg(reg : regidx) -> bool = {
13+
if encdec_reg(reg)[0] == 0b1
14+
then match rv32load_store_pair_odd_register_reserved_behavior {
15+
LoadStorePair_Fatal => reserved_behavior("Zilsd used odd-numbered register " ^ dec_str(unsigned(encdec_reg(reg)))),
16+
LoadStorePair_Illegal => return false,
17+
};
18+
true
19+
}
20+
21+
/* ****************************************************************** */
22+
union clause instruction = ZILSD_LD : (bits(12), regidx, regidx)
23+
24+
$[wavedrom "offset[11:5] src base _ width imm[4:0] STORE"]
25+
mapping clause encdec = ZILSD_LD(imm, rs1, rd)
26+
<-> imm @ encdec_reg(rs1) @ 0b011 @ encdec_reg(rd) @ 0b0000011
27+
when currentlyEnabled(Ext_Zilsd) & validZilsdReg(rd)
28+
29+
function clause execute ZILSD_LD(imm, rs1, rd) = {
30+
assert(xlen == 32);
31+
match vmem_read(rs1, sign_extend(imm), 4, Load(Data), false, false, false) {
32+
Ok(lo) => {
33+
match vmem_read(rs1, sign_extend(imm + 4), 4, Load(Data), false, false, false) {
34+
Ok(hi) => { X_pair(rd) = hi @ lo; RETIRE_SUCCESS },
35+
Err(e) => e,
36+
}
37+
},
38+
Err(e) => e,
39+
}
40+
}
41+
mapping clause assembly = ZILSD_LD(imm, rs1, rd) <-> "ld" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_signed_12(imm) ^ "(" ^ reg_name(rs1) ^ ")"
42+
43+
44+
/* ****************************************************************** */
45+
union clause instruction = ZILSD_SD : (bits(12), regidx, regidx)
46+
47+
$[wavedrom "offset[11:0] base _ width dest LOAD"]
48+
mapping clause encdec = ZILSD_SD(imm7 @ imm5, rs2, rs1)
49+
<-> imm7 : bits(7) @ encdec_reg(rs2) @ encdec_reg(rs1) @ 0b011 @ imm5 : bits(5) @ 0b0100011
50+
when currentlyEnabled(Ext_Zilsd) & validZilsdReg(rs2)
51+
52+
function clause execute ZILSD_SD(imm, rs2, rs1) = {
53+
assert(xlen == 32);
54+
let value = X_pair(rs2);
55+
match vmem_write(rs1, sign_extend(imm), 4, value[31 .. 0], Load(Data), false, false, false) {
56+
Ok(_) => {
57+
match vmem_write(rs1, sign_extend(imm + 4), 4, value[63 .. 32], Load(Data), false, false, false) {
58+
Ok(_) => RETIRE_SUCCESS,
59+
Err(e) => e,
60+
}
61+
},
62+
Err(e) => e,
63+
}
64+
}
65+
66+
mapping clause assembly = ZILSD_SD(offset, rs2, rs1) <-> "sd" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_signed_12(offset) ^ "(" ^ reg_name(rs1) ^ ")"

‎model/postlude/validate_config.sail‎

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Original file line numberDiff line numberDiff line change
@@ -325,6 +325,27 @@ private function check_stateen_config() -> bool = {
325325
valid
326326
}
327327

328+
private function check_required_zilsd_zclsd_option() -> bool = {
329+
var valid : bool = true;
330+
if xlen != 32 & (hartSupports(Ext_Zilsd) | hartSupports(Ext_Zclsd)) then {
331+
valid = false;
332+
print_endline("Zilsd and Zclsd are only available on RV32");
333+
};
334+
if hartSupports(Ext_Zclsd) & not(hartSupports(Ext_Zilsd)) then {
335+
valid = false;
336+
print_endline("The Zclsd extensions is enabled but Zilsd is disabled: supporting Zclsd requires Zilsd.");
337+
};
338+
if hartSupports(Ext_Zclsd) & not(hartSupports(Ext_Zca)) then {
339+
valid = false;
340+
print_endline("The Zclsd extensions is enabled but Zca is disabled: supporting Zclsd requires Zca.");
341+
};
342+
if (hartSupports(Ext_Zclsd) & hartSupports(Ext_Zcf)) then {
343+
valid = false;
344+
print_endline("Both Zclsd and Zcf extensions are enabled: Zclsd is incompatible with Zcf.");
345+
};
346+
valid
347+
}
348+
328349
function config_is_valid() -> bool = {
329350
check_privs()
330351
& check_mmu_config()
@@ -335,4 +356,5 @@ function config_is_valid() -> bool = {
335356
& check_misc_extension_dependencies()
336357
& check_extension_param_constraints()
337358
& check_stateen_config()
359+
& check_required_zilsd_zclsd_option()
338360
}

‎model/riscv.sail_project‎

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Original file line numberDiff line numberDiff line change
@@ -369,6 +369,11 @@ extensions {
369369
}
370370
}
371371

372+
Zclsd {
373+
requires core, sys, Zilsd
374+
files extensions/Zclsd/zclsd_insts.sail
375+
}
376+
372377
Zicond {
373378
requires core
374379

@@ -452,6 +457,11 @@ extensions {
452457
files extensions/Zihintpause/zihintpause_insts.sail
453458
}
454459

460+
Zilsd {
461+
requires core, sys, I_insts
462+
files extensions/Zilsd/zilsd_insts.sail
463+
}
464+
455465
Ssqosid {
456466
requires core
457467
files extensions/Ssqosid/ssqosid.sail

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