Implement callbacks for state-changing events (#494)

Add a callback API for register, PC and CSR updates, memory writes and
traps. This is used for logging and RVFI instead of embedding that code
in the model itself.

Co-authored-by: Jordan Carlin <jordanmcarlin@gmail.com>
Co-authored-by: Tim Hutt <timothy.hutt@codasip.com>

Author: 3 people

c_emulator/CMakeLists.txt

@@ -1,4 +1,6 @@
 set(EMULATOR_COMMON_SRCS
+    riscv_callbacks.cpp
+    riscv_callbacks.h
     riscv_config.h
     riscv_platform.cpp
     riscv_platform.h

c_emulator/riscv_callbacks.cpp

@@ -0,0 +1,136 @@
+#include "riscv_callbacks.h"
+#include "riscv_config.h"
+#include "riscv_platform_impl.h"
+#include <stdlib.h>
+#include <vector>
+#include <inttypes.h>
+
+bool config_enable_rvfi = true; // Only used if RVFI_DII is defined
+
+void print_lbits_hex(lbits val, int length = 0)
+{
+  if (length == 0) {
+    length = val.len;
+  }
+  std::vector<uint8_t> data(length);
+  mpz_export(data.data(), nullptr, -1, 1, 0, 0, *val.bits);
+  for (int i = length - 1; i >= 0; --i) {
+    fprintf(trace_log, "%02" PRIX8, data[i]);
+  }
+  fprintf(trace_log, "\n");
+}
+
+// Implementations of default callbacks for trace printing and RVFI.
+// The model assumes that these functions do not change the state of the model.
+unit mem_write_callback(uint64_t paddr, uint64_t width, lbits value)
+{
+  if (config_print_mem_access) {
+    fprintf(trace_log, "mem[0x%016" PRIX64 "] <- 0x", paddr);
+    print_lbits_hex(value, width);
+  }
+#ifdef RVFI_DII
+  if (config_enable_rvfi) {
+    zrvfi_write(paddr, width, value);
+  }
+#endif
+  return UNIT;
+}
+
+unit mem_read_callback(const char *type, uint64_t paddr, uint64_t width,
+                       lbits value)
+{
+  if (config_print_mem_access) {
+    fprintf(trace_log, "mem[%s,0x%016" PRIX64 "] -> 0x", type, paddr);
+    print_lbits_hex(value, width);
+  }
+#ifdef RVFI_DII
+  if (config_enable_rvfi) {
+    sail_int len;
+    CREATE(sail_int)(&len);
+    CONVERT_OF(sail_int, mach_int)(&len, width);
+    zrvfi_read(paddr, len, value);
+    KILL(sail_int)(&len);
+  }
+#endif
+  return UNIT;
+}
+
+unit mem_exception_callback(uint64_t paddr, uint64_t num_of_exception)
+{
+  (void)num_of_exception;
+#ifdef RVFI_DII
+  if (config_enable_rvfi) {
+    zrvfi_mem_exception(paddr);
+  }
+#else
+  (void)paddr;
+#endif
+  return UNIT;
+}
+
+unit xreg_write_callback(unsigned reg, uint64_t value)
+{
+  if (config_print_reg) {
+    fprintf(trace_log, "x%d <- 0x%016" PRIX64 "\n", reg, value);
+  }
+#ifdef RVFI_DII
+  if (config_enable_rvfi) {
+    zrvfi_wX(reg, value);
+  }
+#endif
+  return UNIT;
+}
+
+unit freg_write_callback(unsigned reg, uint64_t value)
+{
+  // TODO: will only print bits; should we print in floating point format?
+  if (config_print_reg) {
+    fprintf(trace_log, "f%d <- 0x%016" PRIX64 "\n", reg, value);
+  }
+  return UNIT;
+}
+
+unit csr_full_write_callback(const_sail_string csr_name, unsigned reg,
+                             uint64_t value)
+{
+  if (config_print_reg) {
+    fprintf(trace_log, "CSR %s (0x%03X) <- 0x%016" PRIX64 "\n", csr_name, reg,
+            value);
+  }
+  return UNIT;
+}
+
+unit csr_full_read_callback(const_sail_string csr_name, unsigned reg,
+                            uint64_t value)
+{
+  if (config_print_reg) {
+    fprintf(trace_log, "CSR %s (0x%03X) -> 0x%016" PRIX64 "\n", csr_name, reg,
+            value);
+  }
+  return UNIT;
+}
+
+unit vreg_write_callback(unsigned reg, lbits value)
+{
+  if (config_print_reg) {
+    fprintf(trace_log, "v%d <- ", reg);
+    print_lbits_hex(value);
+  }
+  return UNIT;
+}
+
+unit pc_write_callback(uint64_t value)
+{
+  (void)value;
+  return UNIT;
+}
+
+unit trap_callback(unit)
+{
+#ifdef RVFI_DII
+  if (config_enable_rvfi) {
+    zrvfi_trap();
+  }
+#endif
+  return UNIT;
+}

c_emulator/riscv_callbacks.h

@@ -0,0 +1,36 @@
+#pragma once
+#include "sail.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+unit mem_write_callback(uint64_t paddr, uint64_t width, lbits value);
+unit mem_read_callback(const char *type, uint64_t paddr, uint64_t width,
+                       lbits value);
+unit mem_exception_callback(uint64_t paddr, uint64_t num_of_exception);
+unit xreg_write_callback(unsigned reg, uint64_t value);
+unit freg_write_callback(unsigned reg, uint64_t value);
+// `full` indicates that the name and index of the CSR are provided.
+// 64 bit CSRs use a long_csr_write_callback Sail function that automatically
+// makes two csr_full_write_callback calls on RV32.
+unit csr_full_write_callback(const_sail_string csr_name, unsigned reg,
+                             uint64_t value);
+unit csr_full_read_callback(const_sail_string csr_name, unsigned reg,
+                            uint64_t value);
+unit vreg_write_callback(unsigned reg, lbits value);
+unit pc_write_callback(uint64_t value);
+unit trap_callback(unit);
+
+#ifdef RVFI_DII
+// TODO: Move these implementations to C.
+unit zrvfi_write(uint64_t paddr, int64_t width, lbits value);
+unit zrvfi_read(uint64_t paddr, sail_int width, lbits value);
+unit zrvfi_mem_exception(uint64_t paddr);
+unit zrvfi_wX(int64_t reg, uint64_t value);
+unit zrvfi_trap();
+#endif
+
+#ifdef __cplusplus
+}
+#endif

c_emulator/riscv_prelude.cpp

@@ -22,20 +22,6 @@ unit print_step(unit)
   return UNIT;
 }
 
-unit print_reg(sail_string s)
-{
-  if (config_print_reg)
-    fprintf(trace_log, "%s\n", s);
-  return UNIT;
-}
-
-unit print_mem_access(sail_string s)
-{
-  if (config_print_mem_access)
-    fprintf(trace_log, "%s\n", s);
-  return UNIT;
-}
-
 unit print_platform(sail_string s)
 {
   if (config_print_platform)
@@ -45,20 +31,10 @@ unit print_platform(sail_string s)
 
 bool get_config_print_instr(unit)
 {
-  return (config_print_instr) ? true : false;
-}
-
-bool get_config_print_reg(unit)
-{
-  return (config_print_reg) ? true : false;
-}
-
-bool get_config_print_mem(unit)
-{
-  return (config_print_mem_access) ? true : false;
+  return config_print_instr;
 }
 
 bool get_config_print_platform(unit)
 {
-  return (config_print_platform) ? true : false;
+  return config_print_platform;
 }

c_emulator/riscv_prelude.h

@@ -11,13 +11,9 @@ unit print_string(sail_string prefix, sail_string msg);
 
 unit print_instr(sail_string s);
 unit print_step(unit);
-unit print_reg(sail_string s);
-unit print_mem_access(sail_string s);
 unit print_platform(sail_string s);
 
 bool get_config_print_instr(unit);
-bool get_config_print_reg(unit);
-bool get_config_print_mem(unit);
 bool get_config_print_platform(unit);
 
 #ifdef __cplusplus

model/CMakeLists.txt

@@ -155,6 +155,7 @@ foreach (xlen IN ITEMS 32 64)
 
             set(sail_regs_srcs
                 "riscv_csr_begin.sail"
+                "riscv_callbacks.sail"
                 "riscv_reg_type.sail"
                 "riscv_freg_type.sail"
                 "riscv_regs.sail"
@@ -263,6 +264,7 @@ foreach (xlen IN ITEMS 32 64)
                         # Extra #include's.
                         --c-include riscv_prelude.h
                         --c-include riscv_platform.h
+                        --c-include riscv_callbacks.h
                         # Don't dead-code eliminate these functions. These should match the
                         # ones used from riscv_sail.h
                         --c-preserve init_model
@@ -283,6 +285,11 @@ foreach (xlen IN ITEMS 32 64)
                         --c-preserve rvfi_halt_exec_packet
                         --c-preserve print_instr_packet
                         --c-preserve print_rvfi_exec
+                        --c-preserve rvfi_write
+                        --c-preserve rvfi_read
+                        --c-preserve rvfi_mem_exception
+                        --c-preserve rvfi_wX
+                        --c-preserve rvfi_trap
                         # Input files.
                         ${sail_srcs}
                 )

model/prelude.sail

@@ -62,23 +62,16 @@ overload max = {max_int}
 val print_string = pure "print_string" : (string, string) -> unit
 
 val print_instr    = pure {interpreter: "print_endline", c: "print_instr", lem: "print_dbg", _: "print_endline"} : string -> unit
-val print_reg      = pure {interpreter: "print_endline", c: "print_reg", lem: "print_dbg", _: "print_endline"} : string -> unit
-val print_mem      = pure {interpreter: "print_endline", c: "print_mem_access", lem: "print_dbg", _: "print_endline"} : string -> unit
 val print_platform = pure {interpreter: "print_endline", c: "print_platform", lem: "print_dbg", _: "print_endline"} : string -> unit
 
 val print_step = pure {c: "print_step"} : unit -> unit
 
 function print_step() = ()
 
 val get_config_print_instr = pure {c:"get_config_print_instr"} : unit -> bool
-val get_config_print_reg = pure {c:"get_config_print_reg"} : unit -> bool
-val get_config_print_mem = pure {c:"get_config_print_mem"} : unit -> bool
-
 val get_config_print_platform = pure {c:"get_config_print_platform"} : unit -> bool
 // defaults for other backends
 function get_config_print_instr () = false
-function get_config_print_reg () = false
-function get_config_print_mem () = false
 function get_config_print_platform () = false
 
 val sign_extend : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m)

model/riscv_callbacks.sail

@@ -0,0 +1,44 @@
+/*=======================================================================================*/
+/*  This Sail RISC-V architecture model, comprising all files and                        */
+/*  directories except where otherwise noted is subject the BSD                          */
+/*  two-clause license in the LICENSE file.                                              */
+/*                                                                                       */
+/*  SPDX-License-Identifier: BSD-2-Clause                                                */
+/*=======================================================================================*/
+
+// Callbacks for state-changing events
+val mem_write_callback = pure {c: "mem_write_callback"} : forall 'n, 0 < 'n <= max_mem_access . (/* addr */ physaddrbits, /* width */ int('n), /* value */ bits(8 * 'n)) -> unit
+val mem_read_callback = pure {c: "mem_read_callback"} : forall 'n, 0 < 'n <= max_mem_access . (/* access type */ string, /* addr */ physaddrbits, /* width */ int('n), /* value */ bits(8 * 'n)) -> unit
+val mem_exception_callback = pure {c: "mem_exception_callback"} : forall 'n, 0 <= 'n < xlen . (/* addr */ physaddrbits, /* num_of_ExceptionType */ int('n)) -> unit
+val pc_write_callback = pure {c: "pc_write_callback"} : xlenbits -> unit
+val xreg_write_callback = pure {c: "xreg_write_callback"} : (regidx, xlenbits) -> unit
+val csr_full_write_callback = pure {c: "csr_full_write_callback"} : (string, csreg, xlenbits) -> unit
+val csr_full_read_callback = pure {c: "csr_full_read_callback"} : (string, csreg, xlenbits) -> unit
+val trap_callback = pure {c: "trap_callback"} : unit -> unit
+
+// Overloads for easier use of callbacks
+function csr_name_write_callback(name : string, value : xlenbits) -> unit = {
+  let csr = csr_name_map(name);
+  csr_full_write_callback(name, csr, value);
+}
+function csr_id_write_callback(csr : csreg, value : xlenbits) -> unit = {
+  let name = csr_name_map(csr);
+  csr_full_write_callback(name, csr, value);
+}
+function csr_name_read_callback(name : string, value : xlenbits) -> unit = {
+  let csr = csr_name_map(name);
+  csr_full_read_callback(name, csr, value);
+}
+function csr_id_read_callback(csr : csreg, value : xlenbits) -> unit = {
+  let name = csr_name_map(csr);
+  csr_full_read_callback(name, csr, value);
+}
+
+overload csr_write_callback = {csr_name_write_callback, csr_id_write_callback, csr_full_write_callback}
+overload csr_read_callback = {csr_name_read_callback, csr_id_read_callback, csr_full_read_callback}
+
+function long_csr_write_callback(name : string, name_high : string, value : bits(64)) -> unit = {
+  csr_write_callback(name, value[xlen - 1 .. 0]);
+  if xlen == 32
+  then csr_write_callback(name_high, value[63 .. 32]);
+}

model/riscv_fdext_regs.sail

@@ -55,6 +55,7 @@ function nan_unbox(m, x) = if 'n == 'm then x else (
 newtype fregidx = Fregidx : bits(5)
 newtype fregno = Fregno : range(0, 31)
 function fregidx_to_fregno (Fregidx(b) : fregidx) -> fregno = Fregno(unsigned(b))
+function fregno_to_fregidx (Fregno(b) : fregno) -> fregidx = Fregidx(to_bits(5, b))
 function fregidx_offset(Fregidx(r) : fregidx, o : bits(5)) -> fregidx = Fregidx(r + o)
 function fregidx_bits(Fregidx(r) : fregidx) -> bits(5) = r
 
@@ -69,6 +70,8 @@ function fregidx_to_regidx (Fregidx(b) : fregidx) -> regidx =
 
 mapping encdec_freg : fregidx <-> bits(5) = { Fregidx(r) <-> r }
 
+val freg_write_callback = pure {c: "freg_write_callback"} : (fregidx, flenbits) -> unit
+
 register f0  : fregtype
 register f1  : fregtype
 register f2  : fregtype
@@ -106,6 +109,7 @@ function dirty_fd_context() -> unit = {
   assert(hartSupports(Ext_F));
   mstatus[FS] = extStatus_to_bits(Dirty);
   mstatus[SD] = 0b1;
+  long_csr_write_callback("mstatus", "mstatush", mstatus.bits);
 }
 
 function dirty_fd_context_if_present() -> unit = {
@@ -193,12 +197,8 @@ function wF (Fregno(r) : fregno, in_v : flenbits) -> unit = {
     _  => assert(false, "invalid floating point register number")
   };
 
+  freg_write_callback(fregno_to_fregidx(Fregno(r)), in_v);
   dirty_fd_context();
-
-  if   get_config_print_reg()
-  then
-      /* TODO: will only print bits; should we print in floating point format? */
-      print_reg("f" ^ dec_str(r) ^ " <- " ^ FRegStr(v));
 }
 
 function rF_bits(i: fregidx) -> flenbits = rF(fregidx_to_fregno(i))