|
| 1 | +/*=======================================================================================*/ |
| 2 | +/* This Sail RISC-V architecture model, comprising all files and */ |
| 3 | +/* directories except where otherwise noted is subject the BSD */ |
| 4 | +/* two-clause license in the LICENSE file. */ |
| 5 | +/* */ |
| 6 | +/* SPDX-License-Identifier: BSD-2-Clause */ |
| 7 | +/*=======================================================================================*/ |
| 8 | + |
| 9 | +function clause currentlyEnabled(Ext_Zilsd) = hartSupports(Ext_Zilsd) & xlen == 32 |
| 10 | + |
| 11 | +/* ****************************************************************** */ |
| 12 | +union clause instruction = ZILSD_LD : (bits(12), regidx, regidx) |
| 13 | + |
| 14 | +$[wavedrom "offset[11:5] src base _ width imm[4:0] STORE"] |
| 15 | +mapping clause encdec = ZILSD_LD(imm, rs1, rd) |
| 16 | + <-> imm @ encdec_reg(rs1) @ 0b011 @ encdec_reg(rd) @ 0b0000011 |
| 17 | + when currentlyEnabled(Ext_Zilsd) & not(bit_to_bool(encdec_reg(rd)[0])) |
| 18 | + |
| 19 | +private function load_imm(vaddr: virtaddr, width : word_width, rd : regidx) -> option(ExceptionType) = { |
| 20 | + assert(width <= xlen_bytes); |
| 21 | + |
| 22 | + if check_misaligned(vaddr, width) |
| 23 | + then Some(E_Load_Addr_Align()) |
| 24 | + else match translateAddr(vaddr, Load(Data)) { |
| 25 | + Err(e, _) => Some(e), |
| 26 | + Ok(paddr, _) => { |
| 27 | + match mem_read(Load(Data), paddr, width, false, false, false) { |
| 28 | + Ok(result) => { X(rd) = extend_value(false, result); None() }, |
| 29 | + Err(e) => Some(e), |
| 30 | + } |
| 31 | + }, |
| 32 | + } |
| 33 | +} |
| 34 | + |
| 35 | +function clause execute ZILSD_LD(imm, rs1, rd) = { |
| 36 | + if rd == zreg then { |
| 37 | + return RETIRE_SUCCESS; |
| 38 | + }; |
| 39 | + let base_addr = X(rs1); |
| 40 | + let vaddr = Virtaddr(base_addr + sign_extend(imm)); |
| 41 | + match load_imm(vaddr, 4, rd) { |
| 42 | + Some(e) => Memory_Exception(vaddr, e), |
| 43 | + None() => { |
| 44 | + let vaddr = Virtaddr(base_addr + sign_extend(imm + 4)); |
| 45 | + match load_imm(vaddr, 4, rd+1) { |
| 46 | + Some(e) => Memory_Exception(vaddr, e), |
| 47 | + None() => RETIRE_SUCCESS, |
| 48 | + } |
| 49 | + } |
| 50 | + } |
| 51 | +} |
| 52 | +mapping clause assembly = ZILSD_LD(imm, rs1, rd) <-> "ld" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_signed_12(imm) ^ "(" ^ reg_name(rs1) ^ ")" |
| 53 | + |
| 54 | + |
| 55 | +/* ****************************************************************** */ |
| 56 | +union clause instruction = ZILSD_SD : (bits(12), regidx, regidx) |
| 57 | + |
| 58 | +$[wavedrom "offset[11:0] base _ width dest LOAD"] |
| 59 | +mapping clause encdec = ZILSD_SD(imm7 @ imm5, rs2, rs1) |
| 60 | + <-> imm7 : bits(7) @ encdec_reg(rs2) @ encdec_reg(rs1) @ 0b011 @ imm5 : bits(5) @ 0b0100011 |
| 61 | + when currentlyEnabled(Ext_Zilsd) & not(bit_to_bool(encdec_reg(rs2)[0])) |
| 62 | + |
| 63 | +private function store_imm(vaddr: virtaddr, width : word_width, rs2_val : xlenbits) -> option(ExceptionType) = { |
| 64 | + assert(width <= xlen_bytes); |
| 65 | + if check_misaligned(vaddr, width) |
| 66 | + then Some(E_SAMO_Addr_Align()) |
| 67 | + else match translateAddr(vaddr, Store(Data)) { |
| 68 | + Err(e, _) => Some(e), |
| 69 | + Ok(paddr, _) => match mem_write_ea(paddr, width, false, false, false) { |
| 70 | + Err(e) => Some(e), |
| 71 | + Ok(_) => match mem_write_value(paddr, width, rs2_val[width * 8 - 1 .. 0], false, false, false) { |
| 72 | + Ok(true) => None(), |
| 73 | + Ok(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), |
| 74 | + Err(e) => Some(e) |
| 75 | + } |
| 76 | + } |
| 77 | + } |
| 78 | +} |
| 79 | + |
| 80 | +function clause execute ZILSD_SD(imm, rs2, rs1) = { |
| 81 | + let base_addr = X(rs1); |
| 82 | + let rs2_val = X(rs2); |
| 83 | + let rs2_pair_val = if rs2 != zreg then X(rs2+1) else rs2_val; |
| 84 | + |
| 85 | + let vaddr = Virtaddr(base_addr + sign_extend(imm)); |
| 86 | + match store_imm(vaddr, 4, rs2_val) { |
| 87 | + Some(e) => Memory_Exception(vaddr, e), |
| 88 | + None() => { |
| 89 | + let vaddr = Virtaddr(base_addr + sign_extend(imm + 4)); |
| 90 | + match store_imm(vaddr, 4, rs2_pair_val) { |
| 91 | + Some(e) => Memory_Exception(vaddr, e), |
| 92 | + None() => RETIRE_SUCCESS, |
| 93 | + } |
| 94 | + } |
| 95 | + } |
| 96 | +} |
| 97 | + |
| 98 | +mapping clause assembly = ZILSD_SD(offset, rs2, rs1) <-> "sd" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_signed_12(offset) ^ "(" ^ reg_name(rs1) ^ ")" |
0 commit comments