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kseniadobrovolskayakseniadobrovolskaya
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Implementing callbacks in sail-riscv for state-changing events
 Pushed all the rv_enable_callbacks into the callback functions.
1 parent 0f53467 commit be696b8

20 files changed

+143
-166
lines changed

‎Makefile‎

Lines changed: 2 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -287,32 +287,6 @@ rvfi: c_emulator/riscv_rvfi_$(ARCH)
287287
c_emulator/riscv_sim_$(ARCH): generated_definitions/c/riscv_model_$(ARCH).c $(C_INCS) $(C_SRCS) $(SOFTFLOAT_LIBS) Makefile
288288
$(CC) -g $(C_WARNINGS) $(C_FLAGS) $< $(C_SRCS) $(SAIL_LIB_DIR)/*.c $(C_LIBS) -o $@
289289

290-
# Note: We have to add -c_preserve since the functions might be optimized out otherwise
291-
rvfi_preserve_fns=-c_preserve rvfi_set_instr_packet \
292-
-c_preserve rvfi_get_cmd \
293-
-c_preserve rvfi_get_insn \
294-
-c_preserve rvfi_get_v2_trace_size \
295-
-c_preserve rvfi_get_v2_support_packet \
296-
-c_preserve rvfi_get_exec_packet_v1 \
297-
-c_preserve rvfi_get_exec_packet_v2 \
298-
-c_preserve rvfi_get_mem_data \
299-
-c_preserve rvfi_get_int_data \
300-
-c_preserve rvfi_zero_exec_packet \
301-
-c_preserve rvfi_halt_exec_packet \
302-
-c_preserve print_rvfi_exec \
303-
-c_preserve print_instr_packet \
304-
-c_preserve print_rvfi_exec
305-
306-
# sed -i isn't posix compliant, unfortunately
307-
generated_definitions/c/riscv_rvfi_model_$(ARCH).c: $(SAIL_RVFI_SRCS) model/main.sail Makefile
308-
mkdir -p generated_definitions/c
309-
$(SAIL) $(c_preserve_fns) $(rvfi_preserve_fns) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_RVFI_SRCS) model/main.sail -o $(basename $@)
310-
sed -e '/^[[:space:]]*$$/d' $@ > $@.new
311-
mv $@.new $@
312-
313-
c_emulator/riscv_rvfi_$(ARCH): generated_definitions/c/riscv_rvfi_model_$(ARCH).c $(C_INCS) $(C_SRCS) $(SOFTFLOAT_LIBS) Makefile
314-
$(CC) -g $(C_WARNINGS) $(C_FLAGS) $< -DRVFI_DII $(C_SRCS) $(SAIL_LIB_DIR)/*.c $(C_LIBS) -o $@
315-
316290
# Note: We have to add -c_preserve since the functions might be optimized out otherwise
317291
rvfi_preserve_fns=-c_preserve rvfi_set_instr_packet \
318292
-c_preserve rvfi_get_cmd \
@@ -327,6 +301,7 @@ rvfi_preserve_fns=-c_preserve rvfi_set_instr_packet \
327301
-c_preserve rvfi_halt_exec_packet \
328302
-c_preserve rvfi_write \
329303
-c_preserve rvfi_read \
304+
-c_preserve rvfi_mem_exception \
330305
-c_preserve rvfi_wX \
331306
-c_preserve print_rvfi_exec \
332307
-c_preserve print_instr_packet \
@@ -340,7 +315,7 @@ generated_definitions/c/riscv_rvfi_model_$(ARCH).c: $(SAIL_RVFI_SRCS) model/main
340315
mv $@.new $@
341316

342317
c_emulator/riscv_rvfi_$(ARCH): generated_definitions/c/riscv_rvfi_model_$(ARCH).c $(C_INCS) $(C_SRCS) $(SOFTFLOAT_LIBS) Makefile
343-
gcc -g $(C_WARNINGS) $(C_FLAGS) $< -DRVFI_DII $(C_SRCS) $(SAIL_LIB_DIR)/*.c $(C_LIBS) -o $@
318+
$(CC) -g $(C_WARNINGS) $(C_FLAGS) $< -DRVFI_DII $(C_SRCS) $(SAIL_LIB_DIR)/*.c $(C_LIBS) -o $@
344319

345320
latex: $(SAIL_SRCS) Makefile
346321
mkdir -p generated_definitions/latex

‎c_emulator/riscv_config.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,3 +5,4 @@ extern bool config_print_instr;
55
extern bool config_print_reg;
66
extern bool config_print_mem_access;
77
extern bool config_print_platform;
8+
extern bool rv_enable_callbacks;

‎c_emulator/riscv_default_callbacks.c‎

Lines changed: 9 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,11 @@
11
/* The model assumes that these functions do not change the state of the model.
22
*/
3-
int mem_update_callback(uint64_t addr, uint64_t width, lbits value,
4-
bool is_exception)
5-
{
6-
}
7-
int mem_read_callback(uint64_t addr, uint64_t width, lbits value,
8-
bool is_exception)
9-
{
10-
}
11-
int xreg_update_callback(unsigned reg, uint64_t value) { }
12-
int freg_update_callback(unsigned reg, uint64_t value) { }
13-
int csr_update_callback(const char *reg_name, uint64_t value) { }
14-
int csr_read_callback(const char *reg_name, uint64_t value) { }
15-
int vreg_update_callback(unsigned reg, lbits value) { }
16-
int pc_update_callback(uint64_t value) { }
3+
int mem_write_callback(uint64_t addr, uint64_t width, lbits value) { }
4+
int mem_read_callback(uint64_t addr, uint64_t width, lbits value) { }
5+
int mem_exception_callback(uint64_t addr, uint64_t num_of_exception) { }
6+
int xreg_write_callback(unsigned reg, uint64_t value) { }
7+
int freg_write_callback(unsigned reg, uint64_t value) { }
8+
int csr_write_callback(unsigned reg, uint64_t value) { }
9+
int csr_read_callback(unsigned reg, uint64_t value) { }
10+
int vreg_write_callback(unsigned reg, lbits value) { }
11+
int pc_write_callback(uint64_t value) { }

‎c_emulator/riscv_rvfi_callbacks.c‎

Lines changed: 29 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,27 +1,37 @@
1-
int zrvfi_write(uint64_t addr, int64_t width, lbits value, bool is_exception);
2-
int zrvfi_read(uint64_t addr, sail_int width, lbits value, bool is_exception);
1+
#include "riscv_config.h"
2+
3+
int zrvfi_write(uint64_t addr, int64_t width, lbits value);
4+
int zrvfi_read(uint64_t addr, sail_int width, lbits value);
5+
int zrvfi_mem_exception(uint64_t addr);
36
int zrvfi_wX(int64_t reg, uint64_t value);
47

5-
int mem_update_callback(uint64_t addr, uint64_t width, lbits value,
6-
bool is_exception)
8+
int mem_write_callback(uint64_t addr, uint64_t width, lbits value)
9+
{
10+
if (rv_enable_callbacks)
11+
zrvfi_write(addr, width, value);
12+
}
13+
int mem_read_callback(uint64_t addr, uint64_t width, lbits value)
714
{
8-
zrvfi_write(addr, width, value, is_exception);
15+
if (rv_enable_callbacks) {
16+
sail_int len;
17+
CREATE(sail_int)(&len);
18+
CONVERT_OF(sail_int, mach_int)(&len, width);
19+
zrvfi_read(addr, len, value);
20+
KILL(sail_int)(&len);
21+
}
922
}
10-
int mem_read_callback(uint64_t addr, uint64_t width, lbits value,
11-
bool is_exception)
23+
int mem_exception_callback(uint64_t addr, uint64_t num_of_exception)
1224
{
13-
sail_int len;
14-
CREATE(sail_int)(&len);
15-
CONVERT_OF(sail_int, mach_int)(&len, width);
16-
zrvfi_read(addr, len, value, is_exception);
17-
KILL(sail_int)(&len);
25+
if (rv_enable_callbacks)
26+
zrvfi_mem_exception(addr);
1827
}
19-
int xreg_update_callback(unsigned reg, uint64_t value)
28+
int xreg_write_callback(unsigned reg, uint64_t value)
2029
{
21-
zrvfi_wX(reg, value);
30+
if (rv_enable_callbacks)
31+
zrvfi_wX(reg, value);
2232
}
23-
int freg_update_callback(unsigned reg, uint64_t value) { }
24-
int csr_update_callback(const char *reg_name, uint64_t value) { }
25-
int csr_read_callback(const char *reg_name, uint64_t value) { }
26-
int vreg_update_callback(unsigned reg, lbits value) { }
27-
int pc_update_callback(uint64_t value) { }
33+
int freg_write_callback(unsigned reg, uint64_t value) { }
34+
int csr_write_callback(unsigned reg, uint64_t value) { }
35+
int csr_read_callback(unsigned reg, uint64_t value) { }
36+
int vreg_write_callback(unsigned reg, lbits value) { }
37+
int pc_write_callback(uint64_t value) { }

‎c_emulator/riscv_sail.h‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -52,19 +52,17 @@ extern bool have_exception;
5252

5353
/* Callbacks for state-changing events */
5454

55-
/* Whether need to call the callback functions */
56-
extern bool zrv_enable_callbacks;
5755
/* The model assumes that these functions do not change the state of the model.
5856
*/
59-
int mem_update_callback(uint64_t addr, uint64_t width, lbits value,
60-
bool is_exception);
61-
int mem_read_callback(uint64_t addr, uint64_t width, lbits value,
62-
bool is_exception);
63-
int xreg_update_callback(unsigned reg, uint64_t value);
64-
int freg_update_callback(unsigned reg, uint64_t value);
65-
int csr_update_callback(const char *reg_name, uint64_t value);
66-
int vreg_update_callback(unsigned reg, lbits value);
67-
int pc_update_callback(uint64_t value);
57+
int mem_write_callback(uint64_t addr, uint64_t width, lbits value);
58+
int mem_read_callback(uint64_t addr, uint64_t width, lbits value);
59+
int mem_exception_callback(uint64_t addr, uint64_t num_of_exception);
60+
int xreg_write_callback(unsigned reg, uint64_t value);
61+
int freg_write_callback(unsigned reg, uint64_t value);
62+
int csr_write_callback(unsigned reg, uint64_t value);
63+
int csr_read_callback(unsigned reg, uint64_t value);
64+
int vreg_write_callback(unsigned reg, lbits value);
65+
int pc_write_callback(uint64_t value);
6866

6967
/* machine state */
7068

‎c_emulator/riscv_sim.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,7 @@ bool config_print_reg = true;
8989
bool config_print_mem_access = true;
9090
bool config_print_platform = true;
9191
bool config_print_rvfi = false;
92+
bool rv_enable_callbacks = true;
9293

9394
void set_config_print(char *var, bool val)
9495
{
@@ -98,6 +99,7 @@ void set_config_print(char *var, bool val)
9899
config_print_reg = val;
99100
config_print_platform = val;
100101
config_print_rvfi = val;
102+
rv_enable_callbacks = val;
101103
} else if (strcmp("instr", var) == 0) {
102104
config_print_instr = val;
103105
} else if (strcmp("reg", var) == 0) {

‎model/riscv_csr_ext.sail‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -22,18 +22,3 @@ end ext_read_CSR
2222

2323
function clause ext_write_CSR (_, _) = None()
2424
end ext_write_CSR
25-
26-
function ext_notification_read_CSR (csr : csreg) -> option(xlenbits) = {
27-
let res = ext_read_CSR(csr);
28-
if rv_enable_callbacks then
29-
match res {
30-
Some(value) => csr_read_callback(csr_name_map(csr), value),
31-
None() => (),
32-
};
33-
res
34-
}
35-
36-
function ext_notification_write_CSR (csr : csreg, value : xlenbits) -> unit = {
37-
let res = ext_write_CSR(csr, value);
38-
if rv_enable_callbacks then csr_update_callback(csr_name_map(csr), value)
39-
}

‎model/riscv_fdext_regs.sail‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -155,7 +155,6 @@ function rF (r : regno) -> flenbits = {
155155

156156
function wF (r : regno, in_v : flenbits) -> unit = {
157157
assert(sys_enable_fdext());
158-
if rv_enable_callbacks then freg_update_callback(regno_to_regidx(r), in_v);
159158
let v = fregval_into_freg(in_v);
160159
match r {
161160
0 => f0 = v,
@@ -194,6 +193,8 @@ function wF (r : regno, in_v : flenbits) -> unit = {
194193
};
195194

196195
dirty_fd_context();
196+
197+
freg_write_callback(regno_to_regidx(r), in_v);
197198
}
198199

199200
function rF_bits(i: regidx) -> flenbits = rF(unsigned(i))

‎model/riscv_insts_vext_mem.sail‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -153,22 +153,25 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem)
153153
Ext_DataAddr_Error(e) => {
154154
if i == 0 then { ext_handle_data_check_error(e); return RETIRE_FAIL }
155155
else {
156-
ext_notification_write_CSR(csr_name_map("vl"), to_bits(sizeof(xlen), i));
156+
vl = to_bits(sizeof(xlen), i);
157+
csr_write_callback(csr_name_map("vl"), vl);
157158
trimmed = true
158159
}
159160
},
160161
Ext_DataAddr_OK(vaddr) => {
161162
if check_misaligned(vaddr, width_type) then {
162163
if i == 0 then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
163164
else {
164-
ext_notification_write_CSR(csr_name_map("vl"), to_bits(sizeof(xlen), i));
165+
vl = to_bits(sizeof(xlen), i);
166+
csr_write_callback(csr_name_map("vl"), vl);
165167
trimmed = true
166168
}
167169
} else match translateAddr(vaddr, Read(Data)) {
168170
TR_Failure(e, _) => {
169171
if i == 0 then { handle_mem_exception(vaddr, e); return RETIRE_FAIL }
170172
else {
171-
ext_notification_write_CSR(csr_name_map("vl"), to_bits(sizeof(xlen), i));
173+
vl = to_bits(sizeof(xlen), i);
174+
csr_write_callback(csr_name_map("vl"), vl);
172175
trimmed = true
173176
}
174177
},
@@ -178,7 +181,8 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem)
178181
MemException(e) => {
179182
if i == 0 then { handle_mem_exception(vaddr, e); return RETIRE_FAIL }
180183
else {
181-
ext_notification_write_CSR(csr_name_map("vl"), to_bits(sizeof(xlen), i));
184+
vl = to_bits(sizeof(xlen), i);
185+
csr_write_callback(csr_name_map("vl"), vl);
182186
trimmed = true
183187
}
184188
}

‎model/riscv_insts_vext_vset.sail‎

Lines changed: 27 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -49,10 +49,10 @@ function handle_illegal_vtype() = {
4949
/* Note: Implementations can set vill or trap if the vtype setting is not supported.
5050
* TODO: configuration support for both solutions
5151
*/
52-
let new_vtype = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */
53-
54-
ext_notification_write_CSR(csr_name_map("vtype"), new_vtype);
55-
ext_notification_write_CSR(csr_name_map("vl"), zeros())
52+
vtype.bits = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */
53+
vl = zeros();
54+
csr_write_callback(csr_name_map("vtype"), vtype.bits);
55+
csr_write_callback(csr_name_map("vl"), vl);
5656
}
5757

5858
val calculate_new_vl : (int, int) -> xlenbits
@@ -77,8 +77,7 @@ function clause execute VSETVLI(ma, ta, sew, lmul, rs1, rd) = {
7777
let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori;
7878

7979
/* set vtype */
80-
let new_vtype = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul;
81-
ext_notification_write_CSR(csr_name_map("vtype"), new_vtype);
80+
vtype.bits = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul;
8281

8382
/* check new SEW and LMUL are legal and calculate VLMAX */
8483
let VLEN_pow = get_vlen_pow();
@@ -92,11 +91,11 @@ function clause execute VSETVLI(ma, ta, sew, lmul, rs1, rd) = {
9291
if (rs1 != 0b00000) then { /* normal stripmining */
9392
let rs1_val = X(rs1);
9493
let AVL = unsigned(rs1_val);
95-
ext_notification_write_CSR(csr_name_map("vl"), calculate_new_vl(AVL, VLMAX));
94+
vl = calculate_new_vl(AVL, VLMAX);
9695
X(rd) = vl;
9796
} else if (rd != 0b00000) then { /* set vl to VLMAX */
9897
let AVL = unsigned(ones(sizeof(xlen)));
99-
ext_notification_write_CSR(csr_name_map("vl"), to_bits(sizeof(xlen), VLMAX));
98+
vl = to_bits(sizeof(xlen), VLMAX);
10099
X(rd) = vl;
101100
} else { /* keep existing vl */
102101
let AVL = unsigned(vl);
@@ -105,7 +104,11 @@ function clause execute VSETVLI(ma, ta, sew, lmul, rs1, rd) = {
105104
};
106105

107106
/* reset vstart to 0 */
108-
ext_notification_write_CSR(csr_name_map("vstart"), zeros());
107+
vstart = zeros();
108+
109+
csr_write_callback(csr_name_map("vtype"), vtype.bits);
110+
csr_write_callback(csr_name_map("vl"), vl);
111+
csr_write_callback(csr_name_map("vstart"), zero_extend(vstart));
109112

110113
RETIRE_SUCCESS
111114
}
@@ -125,8 +128,7 @@ function clause execute VSETVL(rs2, rs1, rd) = {
125128
let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori;
126129

127130
/* set vtype */
128-
let new_vtype = X(rs2);
129-
ext_notification_write_CSR(csr_name_map("vtype"), new_vtype);
131+
vtype.bits = X(rs2);
130132

131133
/* check new SEW and LMUL are legal and calculate VLMAX */
132134
let VLEN_pow = get_vlen_pow();
@@ -140,11 +142,11 @@ function clause execute VSETVL(rs2, rs1, rd) = {
140142
if (rs1 != 0b00000) then { /* normal stripmining */
141143
let rs1_val = X(rs1);
142144
let AVL = unsigned(rs1_val);
143-
ext_notification_write_CSR(csr_name_map("vl"), calculate_new_vl(AVL, VLMAX));
145+
vl = calculate_new_vl(AVL, VLMAX);
144146
X(rd) = vl;
145147
} else if (rd != 0b00000) then { /* set vl to VLMAX */
146148
let AVL = unsigned(ones(sizeof(xlen)));
147-
ext_notification_write_CSR(csr_name_map("vl"), to_bits(sizeof(xlen), VLMAX));
149+
vl = to_bits(sizeof(xlen), VLMAX);
148150
X(rd) = vl;
149151
} else { /* keep existing vl */
150152
let AVL = unsigned(vl);
@@ -153,7 +155,11 @@ function clause execute VSETVL(rs2, rs1, rd) = {
153155
};
154156

155157
/* reset vstart to 0 */
156-
ext_notification_write_CSR(csr_name_map("vstart"), zeros());
158+
vstart = zeros();
159+
160+
csr_write_callback(csr_name_map("vtype"), vtype.bits);
161+
csr_write_callback(csr_name_map("vl"), vl);
162+
csr_write_callback(csr_name_map("vstart"), zero_extend(vstart));
157163

158164
RETIRE_SUCCESS
159165
}
@@ -169,8 +175,7 @@ mapping clause encdec = VSETIVLI(ma, ta, sew, lmul, uimm, rd) if extensionEnable
169175

170176
function clause execute VSETIVLI(ma, ta, sew, lmul, uimm, rd) = {
171177
/* set vtype */
172-
let new_vtype = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul;
173-
ext_notification_write_CSR(csr_name_map("vtype"), new_vtype);
178+
vtype.bits = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul;
174179

175180
/* check new SEW and LMUL are legal and calculate VLMAX */
176181
let VLEN_pow = get_vlen_pow();
@@ -182,11 +187,15 @@ function clause execute VSETIVLI(ma, ta, sew, lmul, uimm, rd) = {
182187

183188
/* set vl according to VLMAX and AVL */
184189
let AVL = unsigned(uimm); /* AVL is encoded as 5-bit zero-extended imm in the rs1 field */
185-
ext_notification_write_CSR(csr_name_map("vl"), calculate_new_vl(AVL, VLMAX));
190+
vl = calculate_new_vl(AVL, VLMAX);
186191
X(rd) = vl;
187192

188193
/* reset vstart to 0 */
189-
ext_notification_write_CSR(csr_name_map("vstart"), zeros());
194+
vstart = zeros();
195+
196+
csr_write_callback(csr_name_map("vtype"), vtype.bits);
197+
csr_write_callback(csr_name_map("vl"), vl);
198+
csr_write_callback(csr_name_map("vstart"), zero_extend(vstart));
190199

191200
RETIRE_SUCCESS
192201
}

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