Implementing callbacks in sail-riscv for state-changing events

1. Added callback functions for XRegs, FRegs, VRegs, PC, CSR and memory writes, and CSR and memory reads.
2. Added RVFI and standard trace logging implementation of callbacks.

Co-authored-by: Tim Hutt <timothy.hutt@codasip.com>

Author: jordancarlin

c_emulator/CMakeLists.txt

@@ -1,4 +1,6 @@
 set(EMULATOR_COMMON_SRCS
+    riscv_callbacks.cpp
+    riscv_callbacks.h
     riscv_config.h
     riscv_platform.cpp
     riscv_platform.h

c_emulator/riscv_callbacks.cpp

@@ -0,0 +1,132 @@
+#include "riscv_callbacks.h"
+#include "riscv_config.h"
+#include "riscv_platform_impl.h"
+#include <stdlib.h>
+#include <vector>
+#include <inttypes.h>
+
+void print_lbits_hex(lbits val, int length = 0)
+{
+  if (length == 0) {
+    length = val.len;
+  }
+  std::vector<uint8_t> data(length);
+  mpz_export(data.data(), nullptr, -1, 1, 0, 0, *val.bits);
+  for (int i = length - 1; i >= 0; --i) {
+    fprintf(trace_log, "%02" PRIX8, data[i]);
+  }
+  fprintf(trace_log, "\n");
+}
+
+// Implementations of default callbacks for trace printing and RVFI.
+// The model assumes that these functions do not change the state of the model.
+unit mem_write_callback(uint64_t addr, uint64_t width, lbits value)
+{
+  if (config_print_mem_access) {
+    fprintf(trace_log, "mem[0x%016" PRIX64 "] <- 0x", addr);
+    print_lbits_hex(value, width);
+  }
+#ifdef RVFI_DII
+  if (config_enable_rvfi) {
+    zrvfi_write(addr, width, value);
+  }
+#endif
+  return UNIT;
+}
+
+unit mem_read_callback(const char *type, uint64_t addr, uint64_t width,
+                       lbits value)
+{
+  if (config_print_mem_access) {
+    fprintf(trace_log, "mem[%s,0x%016" PRIX64 "] -> 0x", type, addr);
+    print_lbits_hex(value, width);
+  }
+#ifdef RVFI_DII
+  if (config_enable_rvfi) {
+    sail_int len;
+    CREATE(sail_int)(&len);
+    CONVERT_OF(sail_int, mach_int)(&len, width);
+    zrvfi_read(addr, len, value);
+    KILL(sail_int)(&len);
+  }
+#endif
+  return UNIT;
+}
+
+unit mem_exception_callback(uint64_t addr, uint64_t num_of_exception)
+{
+  (void)num_of_exception;
+#ifdef RVFI_DII
+  if (config_enable_rvfi) {
+    zrvfi_mem_exception(addr);
+  }
+#else
+  (void)addr;
+#endif
+  return UNIT;
+}
+
+unit xreg_write_callback(unsigned reg, uint64_t value)
+{
+  if (config_print_reg) {
+    fprintf(trace_log, "x%d <- 0x%016" PRIX64 "\n", reg, value);
+  }
+#ifdef RVFI_DII
+  if (config_enable_rvfi) {
+    zrvfi_wX(reg, value);
+  }
+#endif
+  return UNIT;
+}
+
+unit freg_write_callback(unsigned reg, uint64_t value)
+{
+  // TODO: will only print bits; should we print in floating point format?
+  if (config_print_reg) {
+    fprintf(trace_log, "f%d <- 0x%016" PRIX64 "\n", reg, value);
+  }
+  return UNIT;
+}
+
+unit csr_write_callback(sail_string csr_name, unsigned reg, uint64_t value)
+{
+  if (config_print_reg) {
+    fprintf(trace_log, "CSR %s (0x%03X) <- 0x%016" PRIX64 "\n", csr_name, reg,
+            value);
+  }
+  return UNIT;
+}
+
+unit csr_read_callback(sail_string csr_name, unsigned reg, uint64_t value)
+{
+  if (config_print_reg) {
+    fprintf(trace_log, "CSR %s (0x%03X) -> 0x%016" PRIX64 "\n", csr_name, reg,
+            value);
+  }
+  return UNIT;
+}
+
+unit vreg_write_callback(unsigned reg, lbits value)
+{
+  if (config_print_reg) {
+    fprintf(trace_log, "v%d <- ", reg);
+    print_lbits_hex(value);
+  }
+  return UNIT;
+}
+
+unit pc_write_callback(uint64_t value)
+{
+  (void)value;
+  return UNIT;
+}
+
+unit trap_callback(unit)
+{
+#ifdef RVFI_DII
+  if (config_enable_rvfi) {
+    zrvfi_trap();
+  }
+#endif
+  return UNIT;
+}

c_emulator/riscv_callbacks.h

@@ -0,0 +1,31 @@
+#pragma once
+#include "sail.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+unit mem_write_callback(uint64_t addr, uint64_t width, lbits value);
+unit mem_read_callback(const char *type, uint64_t addr, uint64_t width,
+                       lbits value);
+unit mem_exception_callback(uint64_t addr, uint64_t num_of_exception);
+unit xreg_write_callback(unsigned reg, uint64_t value);
+unit freg_write_callback(unsigned reg, uint64_t value);
+unit csr_write_callback(sail_string csr_name, unsigned reg, uint64_t value);
+unit csr_read_callback(sail_string csr_name, unsigned reg, uint64_t value);
+unit vreg_write_callback(unsigned reg, lbits value);
+unit pc_write_callback(uint64_t value);
+unit trap_callback(unit);
+
+#ifdef RVFI_DII
+// TODO: Move these implementations to C.
+unit zrvfi_write(uint64_t addr, int64_t width, lbits value);
+unit zrvfi_read(uint64_t addr, sail_int width, lbits value);
+unit zrvfi_mem_exception(uint64_t addr);
+unit zrvfi_wX(int64_t reg, uint64_t value);
+unit zrvfi_trap();
+#endif
+
+#ifdef __cplusplus
+}
+#endif

c_emulator/riscv_config.h

@@ -6,3 +6,4 @@ extern bool config_print_step;
 extern bool config_print_reg;
 extern bool config_print_mem_access;
 extern bool config_print_platform;
+extern bool config_enable_rvfi;

c_emulator/riscv_prelude.cpp

@@ -22,20 +22,6 @@ unit print_step(unit)
   return UNIT;
 }
 
-unit print_reg(sail_string s)
-{
-  if (config_print_reg)
-    fprintf(trace_log, "%s\n", s);
-  return UNIT;
-}
-
-unit print_mem_access(sail_string s)
-{
-  if (config_print_mem_access)
-    fprintf(trace_log, "%s\n", s);
-  return UNIT;
-}
-
 unit print_platform(sail_string s)
 {
   if (config_print_platform)
@@ -45,20 +31,10 @@ unit print_platform(sail_string s)
 
 bool get_config_print_instr(unit)
 {
-  return (config_print_instr) ? true : false;
-}
-
-bool get_config_print_reg(unit)
-{
-  return (config_print_reg) ? true : false;
-}
-
-bool get_config_print_mem(unit)
-{
-  return (config_print_mem_access) ? true : false;
+  return config_print_instr;
 }
 
 bool get_config_print_platform(unit)
 {
-  return (config_print_platform) ? true : false;
+  return config_print_platform;
 }

c_emulator/riscv_prelude.h

@@ -11,13 +11,9 @@ unit print_string(sail_string prefix, sail_string msg);
 
 unit print_instr(sail_string s);
 unit print_step(unit);
-unit print_reg(sail_string s);
-unit print_mem_access(sail_string s);
 unit print_platform(sail_string s);
 
 bool get_config_print_instr(unit);
-bool get_config_print_reg(unit);
-bool get_config_print_mem(unit);
 bool get_config_print_platform(unit);
 
 #ifdef __cplusplus

c_emulator/riscv_sim.cpp

@@ -57,6 +57,7 @@ bool config_print_mem_access = true;
 bool config_print_platform = true;
 bool config_print_rvfi = false;
 bool config_print_step = false;
+bool config_enable_rvfi = true;
 
 void set_config_print(char *var, bool val)
 {
@@ -66,6 +67,7 @@ void set_config_print(char *var, bool val)
     config_print_reg = val;
     config_print_platform = val;
     config_print_rvfi = val;
+    config_enable_rvfi = val;
   } else if (strcmp("instr", var) == 0) {
     config_print_instr = val;
   } else if (strcmp("reg", var) == 0) {

model/CMakeLists.txt

@@ -261,6 +261,7 @@ foreach (xlen IN ITEMS 32 64)
                         # Extra #include's.
                         --c-include riscv_prelude.h
                         --c-include riscv_platform.h
+                        --c-include riscv_callbacks.h
                         # Don't dead-code eliminate these functions. These should match the
                         # ones used from riscv_sail.h
                         --c-preserve init_model
@@ -281,6 +282,12 @@ foreach (xlen IN ITEMS 32 64)
                         --c-preserve rvfi_halt_exec_packet
                         --c-preserve print_instr_packet
                         --c-preserve print_rvfi_exec
+                        --c-preserve rvfi_write
+                        --c-preserve rvfi_read
+                        --c-preserve rvfi_mem_exception
+                        --c-preserve rvfi_wX
+                        --c-preserve rvfi_trap
+                        --c-preserve csr_name_map_forwards
                         # Input files.
                         ${sail_srcs}
                 )

model/prelude.sail

@@ -62,23 +62,16 @@ overload max = {max_int}
 val print_string = pure "print_string" : (string, string) -> unit
 
 val print_instr    = pure {interpreter: "print_endline", c: "print_instr", lem: "print_dbg", _: "print_endline"} : string -> unit
-val print_reg      = pure {interpreter: "print_endline", c: "print_reg", lem: "print_dbg", _: "print_endline"} : string -> unit
-val print_mem      = pure {interpreter: "print_endline", c: "print_mem_access", lem: "print_dbg", _: "print_endline"} : string -> unit
 val print_platform = pure {interpreter: "print_endline", c: "print_platform", lem: "print_dbg", _: "print_endline"} : string -> unit
 
 val print_step = pure {c: "print_step"} : unit -> unit
 
 function print_step() = ()
 
 val get_config_print_instr = pure {c:"get_config_print_instr"} : unit -> bool
-val get_config_print_reg = pure {c:"get_config_print_reg"} : unit -> bool
-val get_config_print_mem = pure {c:"get_config_print_mem"} : unit -> bool
-
 val get_config_print_platform = pure {c:"get_config_print_platform"} : unit -> bool
 // defaults for other backends
 function get_config_print_instr () = false
-function get_config_print_reg () = false
-function get_config_print_mem () = false
 function get_config_print_platform () = false
 
 val sign_extend : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m)

model/riscv_fdext_regs.sail

@@ -55,6 +55,7 @@ function nan_unbox(m, x) = if 'n == 'm then x else (
 newtype fregidx = Fregidx : bits(5)
 newtype fregno = Fregno : range(0, 31)
 function fregidx_to_fregno (Fregidx(b) : fregidx) -> fregno = Fregno(unsigned(b))
+function fregno_to_fregidx (Fregno(b) : fregno) -> fregidx = Fregidx(to_bits(5, b))
 function fregidx_offset(Fregidx(r) : fregidx, o : bits(5)) -> fregidx = Fregidx(r + o)
 function fregidx_bits(Fregidx(r) : fregidx) -> bits(5) = r
 
@@ -69,6 +70,8 @@ function fregidx_to_regidx (Fregidx(b) : fregidx) -> regidx =
 
 mapping encdec_freg : fregidx <-> bits(5) = { Fregidx(r) <-> r }
 
+val freg_write_callback = pure {c: "freg_write_callback"} : (fregidx, flenbits) -> unit
+
 register f0  : fregtype
 register f1  : fregtype
 register f2  : fregtype
@@ -106,6 +109,9 @@ function dirty_fd_context() -> unit = {
   assert(hartSupports(Ext_F));
   mstatus[FS] = extStatus_to_bits(Dirty);
   mstatus[SD] = 0b1;
+  csr_write_callback("mstatus", csr_name_map("mstatus"), mstatus.bits[xlen - 1 .. 0]);
+  if xlen == 32
+  then csr_write_callback("mstatush", csr_name_map("mstatush"), mstatus.bits[63 .. 32]);
 }
 
 function dirty_fd_context_if_present() -> unit = {
@@ -193,12 +199,8 @@ function wF (Fregno(r) : fregno, in_v : flenbits) -> unit = {
     _  => assert(false, "invalid floating point register number")
   };
 
+  freg_write_callback(fregno_to_fregidx(Fregno(r)), in_v);
   dirty_fd_context();
-
-  if   get_config_print_reg()
-  then
-      /* TODO: will only print bits; should we print in floating point format? */
-      print_reg("f" ^ dec_str(r) ^ " <- " ^ FRegStr(v));
 }
 
 function rF_bits(i: fregidx) -> flenbits = rF(fregidx_to_fregno(i))