`medeleg` bit 0 should be controlled by `currentlyEnabled(Ext_Zca)`

[jordancarlin]

See Spike issue here: riscv-software-src/riscv-isa-sim#2230, riscv-software-src/riscv-isa-sim#2232.

Looks like the Sail model has the same issue:

private function legalize_medeleg(_o : Medeleg, v : bits(64)) -> Medeleg = {
  // M-EnvCalls delegation is not supported
  [Mk_Medeleg(v) with MEnvCall = 0b0]
}