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[LegalizeTypes] Don't promote operands to VP extends (llvm#179475)
This is part of the work to remove trivial VP intrinsics. When promoting the result of a VP node, if we need to extend an operand then we also extend it with a VP node. We don't check if the VP node is legal though which will cause crashes if the target doesn't support VP_ZEXT/VP_SEXT. This switches it to use a regular non-VP node to extend instead.
1 parent 785ac3a commit 989f736

27 files changed

+114
-162
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp‎

Lines changed: 27 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -738,18 +738,15 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
738738
// Subtract off the extra leading bits in the bigger type.
739739
SDValue ExtractLeadingBits = DAG.getConstant(
740740
NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl, NVT);
741+
// Zero extend to the promoted type and do the count there.
742+
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
741743

742-
if (!N->isVPOpcode()) {
743-
// Zero extend to the promoted type and do the count there.
744-
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
744+
if (!N->isVPOpcode())
745745
return DAG.getNode(ISD::SUB, dl, NVT,
746746
DAG.getNode(N->getOpcode(), dl, NVT, Op),
747747
ExtractLeadingBits);
748-
}
749748
SDValue Mask = N->getOperand(1);
750749
SDValue EVL = N->getOperand(2);
751-
// Zero extend to the promoted type and do the count there.
752-
SDValue Op = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
753750
return DAG.getNode(ISD::VP_SUB, dl, NVT,
754751
DAG.getNode(N->getOpcode(), dl, NVT, Op, Mask, EVL),
755752
ExtractLeadingBits, Mask, EVL);
@@ -806,14 +803,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
806803
}
807804

808805
// Zero extend to the promoted type and do the count or parity there.
809-
if (!N->isVPOpcode()) {
810-
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
806+
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
807+
if (!N->isVPOpcode())
811808
return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op);
812-
}
813809

814810
SDValue Mask = N->getOperand(1);
815811
SDValue EVL = N->getOperand(2);
816-
SDValue Op = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
817812
return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op, Mask,
818813
EVL);
819814
}
@@ -1483,17 +1478,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) {
14831478
SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
14841479
SDValue LHS = GetPromotedInteger(N->getOperand(0));
14851480
SDValue RHS = N->getOperand(1);
1486-
if (N->getOpcode() != ISD::VP_SHL) {
1487-
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1488-
RHS = ZExtPromotedInteger(RHS);
1489-
1481+
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1482+
RHS = ZExtPromotedInteger(RHS);
1483+
if (N->getOpcode() != ISD::VP_SHL)
14901484
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1491-
}
14921485

14931486
SDValue Mask = N->getOperand(2);
14941487
SDValue EVL = N->getOperand(3);
1495-
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1496-
RHS = VPZExtPromotedInteger(RHS, Mask, EVL);
14971488
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
14981489
Mask, EVL);
14991490
}
@@ -1519,37 +1510,30 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
15191510
}
15201511

15211512
SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1522-
if (N->getNumOperands() == 2) {
1523-
// Sign extend the input.
1524-
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1525-
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1513+
// Sign extend the input.
1514+
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1515+
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1516+
if (N->getNumOperands() == 2)
15261517
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1527-
}
15281518
assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
15291519
assert(N->isVPOpcode() && "Expected VP opcode");
15301520
SDValue Mask = N->getOperand(2);
15311521
SDValue EVL = N->getOperand(3);
1532-
// Sign extend the input.
1533-
SDValue LHS = VPSExtPromotedInteger(N->getOperand(0), Mask, EVL);
1534-
SDValue RHS = VPSExtPromotedInteger(N->getOperand(1), Mask, EVL);
15351522
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
15361523
Mask, EVL);
15371524
}
15381525

15391526
SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1540-
if (N->getNumOperands() == 2) {
1541-
// Zero extend the input.
1542-
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1543-
SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1527+
// Zero extend the input.
1528+
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1529+
SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1530+
if (N->getNumOperands() == 2)
15441531
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1545-
}
15461532
assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
15471533
assert(N->isVPOpcode() && "Expected VP opcode");
15481534
// Zero extend the input.
15491535
SDValue Mask = N->getOperand(2);
15501536
SDValue EVL = N->getOperand(3);
1551-
SDValue LHS = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
1552-
SDValue RHS = VPZExtPromotedInteger(N->getOperand(1), Mask, EVL);
15531537
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
15541538
Mask, EVL);
15551539
}
@@ -1567,41 +1551,31 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
15671551
}
15681552

15691553
SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1554+
// The input value must be properly sign extended.
1555+
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
15701556
SDValue RHS = N->getOperand(1);
1571-
if (N->getOpcode() != ISD::VP_SRA) {
1572-
// The input value must be properly sign extended.
1573-
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1574-
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1575-
RHS = ZExtPromotedInteger(RHS);
1557+
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1558+
RHS = ZExtPromotedInteger(RHS);
1559+
if (N->getOpcode() != ISD::VP_SRA)
15761560
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1577-
}
15781561

15791562
SDValue Mask = N->getOperand(2);
15801563
SDValue EVL = N->getOperand(3);
1581-
// The input value must be properly sign extended.
1582-
SDValue LHS = VPSExtPromotedInteger(N->getOperand(0), Mask, EVL);
1583-
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1584-
RHS = VPZExtPromotedInteger(RHS, Mask, EVL);
15851564
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
15861565
Mask, EVL);
15871566
}
15881567

15891568
SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
15901569
SDValue RHS = N->getOperand(1);
1591-
if (N->getOpcode() != ISD::VP_SRL) {
1592-
// The input value must be properly zero extended.
1593-
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1594-
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1595-
RHS = ZExtPromotedInteger(RHS);
1570+
// The input value must be properly zero extended.
1571+
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1572+
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1573+
RHS = ZExtPromotedInteger(RHS);
1574+
if (N->getOpcode() != ISD::VP_SRL)
15961575
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1597-
}
15981576

15991577
SDValue Mask = N->getOperand(2);
16001578
SDValue EVL = N->getOperand(3);
1601-
// The input value must be properly zero extended.
1602-
SDValue LHS = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
1603-
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1604-
RHS = VPZExtPromotedInteger(RHS, Mask, EVL);
16051579
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
16061580
Mask, EVL);
16071581
}
@@ -1671,7 +1645,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
16711645
SDValue Mask = N->getOperand(3);
16721646
SDValue EVL = N->getOperand(4);
16731647
if (getTypeAction(Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1674-
Amt = VPZExtPromotedInteger(Amt, Mask, EVL);
1648+
Amt = ZExtPromotedInteger(Amt);
16751649
EVT AmtVT = Amt.getValueType();
16761650

16771651
SDLoc DL(N);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h‎

Lines changed: 0 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -273,27 +273,6 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
273273
return DAG.getZeroExtendInReg(Op, dl, OldVT);
274274
}
275275

276-
/// Get a promoted operand and zero extend it to the final size.
277-
SDValue VPSExtPromotedInteger(SDValue Op, SDValue Mask, SDValue EVL) {
278-
EVT OldVT = Op.getValueType();
279-
SDLoc dl(Op);
280-
Op = GetPromotedInteger(Op);
281-
// FIXME: Add VP_SIGN_EXTEND_INREG.
282-
EVT VT = Op.getValueType();
283-
unsigned BitsDiff = VT.getScalarSizeInBits() - OldVT.getScalarSizeInBits();
284-
SDValue ShiftCst = DAG.getShiftAmountConstant(BitsDiff, VT, dl);
285-
SDValue Shl = DAG.getNode(ISD::VP_SHL, dl, VT, Op, ShiftCst, Mask, EVL);
286-
return DAG.getNode(ISD::VP_SRA, dl, VT, Shl, ShiftCst, Mask, EVL);
287-
}
288-
289-
/// Get a promoted operand and zero extend it to the final size.
290-
SDValue VPZExtPromotedInteger(SDValue Op, SDValue Mask, SDValue EVL) {
291-
EVT OldVT = Op.getValueType();
292-
SDLoc dl(Op);
293-
Op = GetPromotedInteger(Op);
294-
return DAG.getVPZeroExtendInReg(Op, Mask, EVL, dl, OldVT);
295-
}
296-
297276
// Promote the given operand V (vector or scalar) according to N's specific
298277
// reduction kind. N must be an integer VECREDUCE_* or VP_REDUCE_*. Returns
299278
// the nominal extension opcode (ISD::(ANY|ZERO|SIGN)_EXTEND) and the

‎llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2504,7 +2504,7 @@ define <vscale x 1 x i9> @vp_ctlz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
25042504
; CHECK: # %bb.0:
25052505
; CHECK-NEXT: li a1, 511
25062506
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2507-
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
2507+
; CHECK-NEXT: vand.vx v8, v8, a1
25082508
; CHECK-NEXT: li a0, 142
25092509
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
25102510
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -2521,7 +2521,7 @@ define <vscale x 1 x i9> @vp_ctlz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
25212521
; CHECK-ZVBB: # %bb.0:
25222522
; CHECK-ZVBB-NEXT: li a1, 511
25232523
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2524-
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
2524+
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1
25252525
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
25262526
; CHECK-ZVBB-NEXT: vadd.vi v8, v8, -7, v0.t
25272527
; CHECK-ZVBB-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2388,7 +2388,7 @@ define <vscale x 1 x i9> @vp_ctpop_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i
23882388
; CHECK: # %bb.0:
23892389
; CHECK-NEXT: li a1, 511
23902390
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2391-
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
2391+
; CHECK-NEXT: vand.vx v8, v8, a1
23922392
; CHECK-NEXT: lui a0, 5
23932393
; CHECK-NEXT: addi a0, a0, 1365
23942394
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
@@ -2414,7 +2414,7 @@ define <vscale x 1 x i9> @vp_ctpop_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i
24142414
; CHECK-ZVBB: # %bb.0:
24152415
; CHECK-ZVBB-NEXT: li a1, 511
24162416
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2417-
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
2417+
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1
24182418
; CHECK-ZVBB-NEXT: vcpop.v v8, v8, v0.t
24192419
; CHECK-ZVBB-NEXT: ret
24202420
%v = call <vscale x 1 x i9> @llvm.vp.ctpop.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,11 +7,12 @@
77
define <8 x i7> @vdiv_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
88
; CHECK-LABEL: vdiv_vv_v8i7:
99
; CHECK: # %bb.0:
10+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
11+
; CHECK-NEXT: vadd.vv v9, v9, v9
12+
; CHECK-NEXT: vadd.vv v8, v8, v8
13+
; CHECK-NEXT: vsra.vi v9, v9, 1
14+
; CHECK-NEXT: vsra.vi v8, v8, 1
1015
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
11-
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
12-
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
13-
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
14-
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
1516
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
1617
; CHECK-NEXT: ret
1718
%v = call <8 x i7> @llvm.vp.sdiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,10 @@ define <8 x i7> @vdivu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
88
; CHECK-LABEL: vdivu_vv_v8i7:
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: li a1, 127
11+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
12+
; CHECK-NEXT: vand.vx v9, v9, a1
13+
; CHECK-NEXT: vand.vx v8, v8, a1
1114
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
12-
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
13-
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
1415
; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
1516
; CHECK-NEXT: ret
1617
%v = call <8 x i7> @llvm.vp.udiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,11 +7,12 @@
77
define <8 x i7> @vmax_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
88
; CHECK-LABEL: vmax_vv_v8i7:
99
; CHECK: # %bb.0:
10+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
11+
; CHECK-NEXT: vadd.vv v9, v9, v9
12+
; CHECK-NEXT: vadd.vv v8, v8, v8
13+
; CHECK-NEXT: vsra.vi v9, v9, 1
14+
; CHECK-NEXT: vsra.vi v8, v8, 1
1015
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
11-
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
12-
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
13-
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
14-
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
1516
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
1617
; CHECK-NEXT: ret
1718
%v = call <8 x i7> @llvm.vp.smax.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,10 @@ define <8 x i7> @vmaxu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
88
; CHECK-LABEL: vmaxu_vv_v8i7:
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: li a1, 127
11+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
12+
; CHECK-NEXT: vand.vx v9, v9, a1
13+
; CHECK-NEXT: vand.vx v8, v8, a1
1114
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
12-
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
13-
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
1415
; CHECK-NEXT: vmaxu.vv v8, v8, v9, v0.t
1516
; CHECK-NEXT: ret
1617
%v = call <8 x i7> @llvm.vp.umax.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,11 +7,12 @@
77
define <8 x i7> @vmin_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
88
; CHECK-LABEL: vmin_vv_v8i7:
99
; CHECK: # %bb.0:
10+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
11+
; CHECK-NEXT: vadd.vv v9, v9, v9
12+
; CHECK-NEXT: vadd.vv v8, v8, v8
13+
; CHECK-NEXT: vsra.vi v9, v9, 1
14+
; CHECK-NEXT: vsra.vi v8, v8, 1
1015
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
11-
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
12-
; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
13-
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
14-
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
1516
; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t
1617
; CHECK-NEXT: ret
1718
%v = call <8 x i7> @llvm.vp.smin.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,10 @@ define <8 x i7> @vminu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
88
; CHECK-LABEL: vminu_vv_v8i7:
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: li a1, 127
11+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
12+
; CHECK-NEXT: vand.vx v9, v9, a1
13+
; CHECK-NEXT: vand.vx v8, v8, a1
1114
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
12-
; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
13-
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
1415
; CHECK-NEXT: vminu.vv v8, v8, v9, v0.t
1516
; CHECK-NEXT: ret
1617
%v = call <8 x i7> @llvm.vp.umin.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)

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