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Rot127Rot127
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librz/arch: sync with latest LLVM Hexagon v79 version. (#4923)
* Sync with latest LLVM Hexagon v79 version. This uses llvm/llvm-project#120983 which is imcomplete (apparently it misses some HVX instructions). But it replaced some imported instructions with the LLVM definitions. * Add newly generate il operations.
1 parent cc97951 commit efbab1d

40 files changed

+173
-173
lines changed

‎librz/arch/isa/hexagon/hexagon_disas.c‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
22
// SPDX-License-Identifier: LGPL-3.0-only
33

4-
// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
5-
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
6-
// Date of code generation: 2024-03-16 06:22:39-05:00
4+
// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
5+
// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
6+
// Date of code generation: 2025-02-21 18:11:59-05:00
77
//========================================
88
// The following code is generated.
99
// Do not edit. Repository of code generator:
@@ -21216,6 +21216,20 @@ static const HexInsnTemplate templates_normal_0x9[] = {
2121621216
.type = RZ_ANALYSIS_OP_TYPE_NULL,
2121721217
.syntax = " = memuh(<<+)",
2121821218
},
21219+
{
21220+
// 10010010000sssssPP1ttttt000ddddd | Rd = memw_phys(Rs,Rt)
21221+
.encoding = { .mask = 0xffe020e0, .op = 0x92002000 },
21222+
.id = HEX_INS_L4_LOADW_PHYS,
21223+
.ops = {
21224+
{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 'd', .syntax = 0 },
21225+
{ .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 's', .syntax = 13 },
21226+
{ .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 't', .syntax = 14 },
21227+
},
21228+
.pred = HEX_NOPRED,
21229+
.cond = RZ_TYPE_COND_AL,
21230+
.type = RZ_ANALYSIS_OP_TYPE_NULL,
21231+
.syntax = " = memw_phys(,)",
21232+
},
2121921233
{
2122021234
// 10011111000iiiiiPP101tti100ddddd | if (!Pt) Rd = memb(Ii)
2122121235
.encoding = { .mask = 0xffe038e0, .op = 0x9f002880 },
@@ -21720,20 +21734,6 @@ static const HexInsnTemplate templates_normal_0x9[] = {
2172021734
.type = RZ_ANALYSIS_OP_TYPE_NULL,
2172121735
.syntax = "dcfetch(+)",
2172221736
},
21723-
{
21724-
// 10010010000sssssPP1ttttt000ddddd | Rd = memw_phys(Rs,Rt)
21725-
.encoding = { .mask = 0xffe020e0, .op = 0x92002000 },
21726-
.id = HEX_INS_IMPORTED_RD_MEMW_PHYS_RS_RT,
21727-
.ops = {
21728-
{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 'd', .syntax = 0 },
21729-
{ .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 's', .syntax = 13 },
21730-
{ .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .isa_id = 't', .syntax = 14 },
21731-
},
21732-
.pred = HEX_NOPRED,
21733-
.cond = RZ_TYPE_COND_AL,
21734-
.type = RZ_ANALYSIS_OP_TYPE_NULL,
21735-
.syntax = " = memw_phys(,)",
21736-
},
2173721737
{ { 0 } },
2173821738
};
2173921739

@@ -24119,28 +24119,28 @@ static const HexInsnTemplate templates_normal_0xa[] = {
2411924119
.syntax = " = dmwait",
2412024120
},
2412124121
{
24122-
// 1010011010100000PP0ttttt00000000 | l2gclean(Rtt)
24123-
.encoding = { .mask = 0xffff20ff, .op = 0xa6a00000 },
24124-
.id = HEX_INS_IMPORTED_L2GCLEAN_RTT,
24122+
// 1010011011000000PP0ttttt00000000 | l2gcleaninv(Rtt)
24123+
.encoding = { .mask = 0xffff20ff, .op = 0xa6c00000 },
24124+
.id = HEX_INS_Y6_L2GCLEANINVPA,
2412524125
.ops = {
24126-
{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .isa_id = 't', .syntax = 9 },
24126+
{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .isa_id = 't', .syntax = 12 },
2412724127
},
2412824128
.pred = HEX_NOPRED,
2412924129
.cond = RZ_TYPE_COND_AL,
2413024130
.type = RZ_ANALYSIS_OP_TYPE_NULL,
24131-
.syntax = "l2gclean()",
24131+
.syntax = "l2gcleaninv()",
2413224132
},
2413324133
{
24134-
// 1010011011000000PP0ttttt00000000 | l2gcleaninv(Rtt)
24135-
.encoding = { .mask = 0xffff20ff, .op = 0xa6c00000 },
24136-
.id = HEX_INS_IMPORTED_L2GCLEANINV_RTT,
24134+
// 1010011010100000PP0ttttt00000000 | l2gclean(Rtt)
24135+
.encoding = { .mask = 0xffff20ff, .op = 0xa6a00000 },
24136+
.id = HEX_INS_Y6_L2GCLEANPA,
2413724137
.ops = {
24138-
{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .isa_id = 't', .syntax = 12 },
24138+
{ .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .isa_id = 't', .syntax = 9 },
2413924139
},
2414024140
.pred = HEX_NOPRED,
2414124141
.cond = RZ_TYPE_COND_AL,
2414224142
.type = RZ_ANALYSIS_OP_TYPE_NULL,
24143-
.syntax = "l2gcleaninv()",
24143+
.syntax = "l2gclean()",
2414424144
},
2414524145
{ { 0 } },
2414624146
};

‎librz/arch/isa/hexagon/hexagon_il.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -879,6 +879,7 @@ RzILOpEffect *hex_il_op_l4_loadrub_ur(HexInsnPktBundle *bundle);
879879
RzILOpEffect *hex_il_op_l4_loadruh_ap(HexInsnPktBundle *bundle);
880880
RzILOpEffect *hex_il_op_l4_loadruh_rr(HexInsnPktBundle *bundle);
881881
RzILOpEffect *hex_il_op_l4_loadruh_ur(HexInsnPktBundle *bundle);
882+
RzILOpEffect *hex_il_op_l4_loadw_phys(HexInsnPktBundle *bundle);
882883
RzILOpEffect *hex_il_op_l4_or_memopb_io(HexInsnPktBundle *bundle);
883884
RzILOpEffect *hex_il_op_l4_or_memoph_io(HexInsnPktBundle *bundle);
884885
RzILOpEffect *hex_il_op_l4_or_memopw_io(HexInsnPktBundle *bundle);
@@ -2021,17 +2022,16 @@ RzILOpEffect *hex_il_op_y6_dmpoll(HexInsnPktBundle *bundle);
20212022
RzILOpEffect *hex_il_op_y6_dmresume(HexInsnPktBundle *bundle);
20222023
RzILOpEffect *hex_il_op_y6_dmstart(HexInsnPktBundle *bundle);
20232024
RzILOpEffect *hex_il_op_y6_dmwait(HexInsnPktBundle *bundle);
2025+
RzILOpEffect *hex_il_op_y6_l2gcleaninvpa(HexInsnPktBundle *bundle);
2026+
RzILOpEffect *hex_il_op_y6_l2gcleanpa(HexInsnPktBundle *bundle);
20242027
RzILOpEffect *hex_il_op_dep_a2_addsat(HexInsnPktBundle *bundle);
20252028
RzILOpEffect *hex_il_op_dep_a2_subsat(HexInsnPktBundle *bundle);
20262029
RzILOpEffect *hex_il_op_dep_s2_packhl(HexInsnPktBundle *bundle);
20272030
RzILOpEffect *hex_il_op_invalid_decode(HexInsnPktBundle *bundle);
20282031
RzILOpEffect *hex_il_op_imported_rd_ss(HexInsnPktBundle *bundle);
2029-
RzILOpEffect *hex_il_op_imported_rd_memw_phys_rs_rt(HexInsnPktBundle *bundle);
20302032
RzILOpEffect *hex_il_op_imported_rdd_sss(HexInsnPktBundle *bundle);
20312033
RzILOpEffect *hex_il_op_imported_sd_rs(HexInsnPktBundle *bundle);
20322034
RzILOpEffect *hex_il_op_imported_sdd_rss(HexInsnPktBundle *bundle);
2033-
RzILOpEffect *hex_il_op_imported_l2gclean_rtt(HexInsnPktBundle *bundle);
2034-
RzILOpEffect *hex_il_op_imported_l2gcleaninv_rtt(HexInsnPktBundle *bundle);
20352035
RzILOpEffect *hex_il_op_sa1_addi(HexInsnPktBundle *bundle);
20362036
RzILOpEffect *hex_il_op_sa1_addrx(HexInsnPktBundle *bundle);
20372037
RzILOpEffect *hex_il_op_sa1_addsp(HexInsnPktBundle *bundle);

‎librz/arch/isa/hexagon/hexagon_il_getter_table.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
22
// SPDX-License-Identifier: LGPL-3.0-only
33

4-
// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
5-
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
6-
// Date of code generation: 2024-03-16 06:22:39-05:00
4+
// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
5+
// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
6+
// Date of code generation: 2025-02-22 07:05:24-05:00
77
//========================================
88
// The following code is generated.
99
// Do not edit. Repository of code generator:
@@ -1199,9 +1199,6 @@ static HexILInsn hex_il_getter_lt[] = {
11991199
{ { (HexILOpGetter)hex_il_op_imported_rd_ss, HEX_IL_INSN_ATTR_INVALID },
12001200
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
12011201
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
1202-
{ { (HexILOpGetter)hex_il_op_imported_rd_memw_phys_rs_rt, HEX_IL_INSN_ATTR_INVALID },
1203-
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
1204-
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
12051202
{ { (HexILOpGetter)hex_il_op_imported_rdd_sss, HEX_IL_INSN_ATTR_INVALID },
12061203
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
12071204
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
@@ -1211,12 +1208,6 @@ static HexILInsn hex_il_getter_lt[] = {
12111208
{ { (HexILOpGetter)hex_il_op_imported_sdd_rss, HEX_IL_INSN_ATTR_INVALID },
12121209
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
12131210
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
1214-
{ { (HexILOpGetter)hex_il_op_imported_l2gclean_rtt, HEX_IL_INSN_ATTR_INVALID },
1215-
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
1216-
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
1217-
{ { (HexILOpGetter)hex_il_op_imported_l2gcleaninv_rtt, HEX_IL_INSN_ATTR_INVALID },
1218-
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
1219-
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
12201211
{ { (HexILOpGetter)hex_il_op_j2_call, HEX_IL_INSN_ATTR_BRANCH },
12211212
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
12221213
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
@@ -2258,6 +2249,9 @@ static HexILInsn hex_il_getter_lt[] = {
22582249
{ { (HexILOpGetter)hex_il_op_l4_loadruh_ur, HEX_IL_INSN_ATTR_MEM_READ },
22592250
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
22602251
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
2252+
{ { (HexILOpGetter)hex_il_op_l4_loadw_phys, HEX_IL_INSN_ATTR_INVALID },
2253+
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
2254+
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
22612255
{ { (HexILOpGetter)hex_il_op_l4_or_memopb_io, HEX_IL_INSN_ATTR_MEM_WRITE | HEX_IL_INSN_ATTR_MEM_READ },
22622256
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
22632257
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
@@ -6705,6 +6699,12 @@ static HexILInsn hex_il_getter_lt[] = {
67056699
{ { (HexILOpGetter)hex_il_op_y6_dmwait, HEX_IL_INSN_ATTR_INVALID },
67066700
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
67076701
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
6702+
{ { (HexILOpGetter)hex_il_op_y6_l2gcleaninvpa, HEX_IL_INSN_ATTR_INVALID },
6703+
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
6704+
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
6705+
{ { (HexILOpGetter)hex_il_op_y6_l2gcleanpa, HEX_IL_INSN_ATTR_INVALID },
6706+
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
6707+
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },
67086708
{ { (HexILOpGetter)hex_il_op_dep_a2_addsat, HEX_IL_INSN_ATTR_INVALID },
67096709
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID },
67106710
{ (HexILOpGetter)NULL, HEX_IL_INSN_ATTR_INVALID } },

‎librz/arch/isa/hexagon/hexagon_insn.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
22
// SPDX-License-Identifier: LGPL-3.0-only
33

4-
// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
5-
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
6-
// Date of code generation: 2024-03-16 06:22:39-05:00
4+
// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
5+
// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
6+
// Date of code generation: 2025-02-21 18:11:59-05:00
77
//========================================
88
// The following code is generated.
99
// Do not edit. Repository of code generator:
@@ -407,12 +407,9 @@ typedef enum {
407407
HEX_INS_G4_TFRGPCP,
408408
HEX_INS_G4_TFRGRCR,
409409
HEX_INS_IMPORTED_RD_SS,
410-
HEX_INS_IMPORTED_RD_MEMW_PHYS_RS_RT,
411410
HEX_INS_IMPORTED_RDD_SSS,
412411
HEX_INS_IMPORTED_SD_RS,
413412
HEX_INS_IMPORTED_SDD_RSS,
414-
HEX_INS_IMPORTED_L2GCLEAN_RTT,
415-
HEX_INS_IMPORTED_L2GCLEANINV_RTT,
416413
HEX_INS_J2_CALL,
417414
HEX_INS_J2_CALLF,
418415
HEX_INS_J2_CALLR,
@@ -760,6 +757,7 @@ typedef enum {
760757
HEX_INS_L4_LOADRUH_AP,
761758
HEX_INS_L4_LOADRUH_RR,
762759
HEX_INS_L4_LOADRUH_UR,
760+
HEX_INS_L4_LOADW_PHYS,
763761
HEX_INS_L4_OR_MEMOPB_IO,
764762
HEX_INS_L4_OR_MEMOPH_IO,
765763
HEX_INS_L4_OR_MEMOPW_IO,
@@ -2386,8 +2384,10 @@ typedef enum {
23862384
HEX_INS_Y6_DMRESUME,
23872385
HEX_INS_Y6_DMSTART,
23882386
HEX_INS_Y6_DMWAIT,
2387+
HEX_INS_Y6_L2GCLEANINVPA,
2388+
HEX_INS_Y6_L2GCLEANPA,
23892389
HEX_INS_DEP_A2_ADDSAT,
23902390
HEX_INS_DEP_A2_SUBSAT,
23912391
HEX_INS_DEP_S2_PACKHL,
23922392
} HexInsnID;
2393-
#endif
2393+
#endif

‎librz/arch/isa/hexagon/il_ops/hexagon_il_A6_ops.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
22
// SPDX-License-Identifier: LGPL-3.0-only
33

4-
// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
5-
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
6-
// Date of code generation: 2024-03-16 06:22:39-05:00
4+
// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
5+
// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
6+
// Date of code generation: 2025-02-22 07:05:24-05:00
77
//========================================
88
// The following code is generated.
99
// Do not edit. Repository of code generator:

‎librz/arch/isa/hexagon/il_ops/hexagon_il_A7_ops.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
22
// SPDX-License-Identifier: LGPL-3.0-only
33

4-
// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
5-
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
6-
// Date of code generation: 2024-03-16 06:22:39-05:00
4+
// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
5+
// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
6+
// Date of code generation: 2025-02-22 07:05:24-05:00
77
//========================================
88
// The following code is generated.
99
// Do not edit. Repository of code generator:

‎librz/arch/isa/hexagon/il_ops/hexagon_il_C2_ops.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
22
// SPDX-License-Identifier: LGPL-3.0-only
33

4-
// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
5-
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
6-
// Date of code generation: 2024-03-16 06:22:39-05:00
4+
// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
5+
// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
6+
// Date of code generation: 2025-02-22 07:05:24-05:00
77
//========================================
88
// The following code is generated.
99
// Do not edit. Repository of code generator:

‎librz/arch/isa/hexagon/il_ops/hexagon_il_C4_ops.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
22
// SPDX-License-Identifier: LGPL-3.0-only
33

4-
// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
5-
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
6-
// Date of code generation: 2024-03-16 06:22:39-05:00
4+
// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
5+
// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
6+
// Date of code generation: 2025-02-22 07:05:24-05:00
77
//========================================
88
// The following code is generated.
99
// Do not edit. Repository of code generator:

‎librz/arch/isa/hexagon/il_ops/hexagon_il_F2_ops.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
22
// SPDX-License-Identifier: LGPL-3.0-only
33

4-
// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
5-
// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
6-
// Date of code generation: 2024-03-16 06:22:39-05:00
4+
// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
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// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
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// Date of code generation: 2025-02-22 07:05:24-05:00
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//========================================
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// The following code is generated.
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// Do not edit. Repository of code generator:

‎librz/arch/isa/hexagon/il_ops/hexagon_il_G4_ops.c‎

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// SPDX-FileCopyrightText: 2021 Rot127 <[email protected]>
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// SPDX-License-Identifier: LGPL-3.0-only
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// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
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// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
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// Date of code generation: 2024-03-16 06:22:39-05:00
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// LLVM commit: c2b89fc9e45d325282b8eb6536f6145282dc3fdf
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// LLVM commit date: 2024-12-23 13:36:28 -0600 (ISO 8601 format)
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// Date of code generation: 2025-02-22 07:05:24-05:00
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//========================================
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// The following code is generated.
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// Do not edit. Repository of code generator:

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