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Merge tag 'drm-intel-fixes-2017-09-20' of git://anongit.freedesktop.org/git/drm-intel into drm-fixes
drm/i915 fixes for 4.14-rc1 Couple fixes for stable: - Fix MIPI panels on BXT. - Fix PCI BARs information on GVT. Plus other fixes: - Fix minimal brightness for BXT, GLK, CFL and CNL. - Fix compilation warning: unused in_vbl - Fix error handling in intel_framebuffer_init * tag 'drm-intel-fixes-2017-09-20' of git://anongit.freedesktop.org/git/drm-intel: drm/i915: Remove unused 'in_vbl' from i915_get_crtc_scanoutpos() drm/i915/cnp: set min brightness from VBT Revert "drm/i915/bxt: Disable device ready before shutdown command" drm/i915/bxt: set min brightness from VBT drm/i915: Fix an error handling in 'intel_framebuffer_init()' drm/i915/gvt: Fix incorrect PCI BARs reporting
2 parents 134dd2e + 99df13b commit c106c7a

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lines changed

5 files changed

+53
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lines changed

‎drivers/gpu/drm/i915/gvt/cfg_space.c‎

Lines changed: 48 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -197,78 +197,65 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu,
197197
static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
198198
void *p_data, unsigned int bytes)
199199
{
200-
unsigned int bar_index =
201-
(rounddown(offset, 8) % PCI_BASE_ADDRESS_0) / 8;
202200
u32 new = *(u32 *)(p_data);
203201
bool lo = IS_ALIGNED(offset, 8);
204202
u64 size;
205203
int ret = 0;
206204
bool mmio_enabled =
207205
vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
206+
struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar;
208207

209-
if (WARN_ON(bar_index >= INTEL_GVT_PCI_BAR_MAX))
210-
return -EINVAL;
211-
208+
/*
209+
* Power-up software can determine how much address
210+
* space the device requires by writing a value of
211+
* all 1's to the register and then reading the value
212+
* back. The device will return 0's in all don't-care
213+
* address bits.
214+
*/
212215
if (new == 0xffffffff) {
213-
/*
214-
* Power-up software can determine how much address
215-
* space the device requires by writing a value of
216-
* all 1's to the register and then reading the value
217-
* back. The device will return 0's in all don't-care
218-
* address bits.
219-
*/
220-
size = vgpu->cfg_space.bar[bar_index].size;
221-
if (lo) {
222-
new = rounddown(new, size);
223-
} else {
224-
u32 val = vgpu_cfg_space(vgpu)[rounddown(offset, 8)];
225-
/* for 32bit mode bar it returns all-0 in upper 32
226-
* bit, for 64bit mode bar it will calculate the
227-
* size with lower 32bit and return the corresponding
228-
* value
216+
switch (offset) {
217+
case PCI_BASE_ADDRESS_0:
218+
case PCI_BASE_ADDRESS_1:
219+
size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1);
220+
intel_vgpu_write_pci_bar(vgpu, offset,
221+
size >> (lo ? 0 : 32), lo);
222+
/*
223+
* Untrap the BAR, since guest hasn't configured a
224+
* valid GPA
229225
*/
230-
if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
231-
new &= (~(size-1)) >> 32;
232-
else
233-
new = 0;
234-
}
235-
/*
236-
* Unmapp & untrap the BAR, since guest hasn't configured a
237-
* valid GPA
238-
*/
239-
switch (bar_index) {
240-
case INTEL_GVT_PCI_BAR_GTTMMIO:
241226
ret = trap_gttmmio(vgpu, false);
242227
break;
243-
case INTEL_GVT_PCI_BAR_APERTURE:
228+
case PCI_BASE_ADDRESS_2:
229+
case PCI_BASE_ADDRESS_3:
230+
size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1);
231+
intel_vgpu_write_pci_bar(vgpu, offset,
232+
size >> (lo ? 0 : 32), lo);
244233
ret = map_aperture(vgpu, false);
245234
break;
235+
default:
236+
/* Unimplemented BARs */
237+
intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false);
246238
}
247-
intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
248239
} else {
249-
/*
250-
* Unmapp & untrap the old BAR first, since guest has
251-
* re-configured the BAR
252-
*/
253-
switch (bar_index) {
254-
case INTEL_GVT_PCI_BAR_GTTMMIO:
255-
ret = trap_gttmmio(vgpu, false);
240+
switch (offset) {
241+
case PCI_BASE_ADDRESS_0:
242+
case PCI_BASE_ADDRESS_1:
243+
/*
244+
* Untrap the old BAR first, since guest has
245+
* re-configured the BAR
246+
*/
247+
trap_gttmmio(vgpu, false);
248+
intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
249+
ret = trap_gttmmio(vgpu, mmio_enabled);
256250
break;
257-
case INTEL_GVT_PCI_BAR_APERTURE:
258-
ret = map_aperture(vgpu, false);
251+
case PCI_BASE_ADDRESS_2:
252+
case PCI_BASE_ADDRESS_3:
253+
map_aperture(vgpu, false);
254+
intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
255+
ret = map_aperture(vgpu, mmio_enabled);
259256
break;
260-
}
261-
intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
262-
/* Track the new BAR */
263-
if (mmio_enabled) {
264-
switch (bar_index) {
265-
case INTEL_GVT_PCI_BAR_GTTMMIO:
266-
ret = trap_gttmmio(vgpu, true);
267-
break;
268-
case INTEL_GVT_PCI_BAR_APERTURE:
269-
ret = map_aperture(vgpu, true);
270-
break;
271-
}
257+
default:
258+
intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
272259
}
273260
}
274261
return ret;
@@ -299,10 +286,7 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
299286
}
300287

301288
switch (rounddown(offset, 4)) {
302-
case PCI_BASE_ADDRESS_0:
303-
case PCI_BASE_ADDRESS_1:
304-
case PCI_BASE_ADDRESS_2:
305-
case PCI_BASE_ADDRESS_3:
289+
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
306290
if (WARN_ON(!IS_ALIGNED(offset, 4)))
307291
return -EINVAL;
308292
return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
@@ -344,7 +328,6 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
344328
struct intel_gvt *gvt = vgpu->gvt;
345329
const struct intel_gvt_device_info *info = &gvt->device_info;
346330
u16 *gmch_ctl;
347-
int i;
348331

349332
memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
350333
info->cfg_space_size);
@@ -371,13 +354,13 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
371354
*/
372355
memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);
373356
memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);
357+
memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);
374358
memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
375359

376-
for (i = 0; i < INTEL_GVT_MAX_BAR_NUM; i++) {
377-
vgpu->cfg_space.bar[i].size = pci_resource_len(
378-
gvt->dev_priv->drm.pdev, i * 2);
379-
vgpu->cfg_space.bar[i].tracked = false;
380-
}
360+
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
361+
pci_resource_len(gvt->dev_priv->drm.pdev, 0);
362+
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
363+
pci_resource_len(gvt->dev_priv->drm.pdev, 2);
381364
}
382365

383366
/**

‎drivers/gpu/drm/i915/i915_irq.c‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -839,7 +839,6 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
839839
pipe);
840840
int position;
841841
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
842-
bool in_vbl = true;
843842
unsigned long irqflags;
844843

845844
if (WARN_ON(!mode->crtc_clock)) {
@@ -922,8 +921,6 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
922921

923922
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
924923

925-
in_vbl = position >= vbl_start && position < vbl_end;
926-
927924
/*
928925
* While in vblank, position will be negative
929926
* counting up towards 0 at vbl_end. And outside

‎drivers/gpu/drm/i915/intel_display.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14030,7 +14030,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
1403014030

1403114031
if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1403214032
DRM_DEBUG_KMS("bad plane %d handle\n", i);
14033-
return -EINVAL;
14033+
goto err;
1403414034
}
1403514035

1403614036
stride_alignment = intel_fb_stride_alignment(fb, i);

‎drivers/gpu/drm/i915/intel_dsi.c‎

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -892,8 +892,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder,
892892
struct intel_crtc_state *old_crtc_state,
893893
struct drm_connector_state *old_conn_state)
894894
{
895-
struct drm_device *dev = encoder->base.dev;
896-
struct drm_i915_private *dev_priv = dev->dev_private;
897895
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
898896
enum port port;
899897

@@ -902,15 +900,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder,
902900
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
903901
intel_panel_disable_backlight(old_conn_state);
904902

905-
/*
906-
* Disable Device ready before the port shutdown in order
907-
* to avoid split screen
908-
*/
909-
if (IS_BROXTON(dev_priv)) {
910-
for_each_dsi_port(port, intel_dsi->ports)
911-
I915_WRITE(MIPI_DEVICE_READY(port), 0);
912-
}
913-
914903
/*
915904
* According to the spec we should send SHUTDOWN before
916905
* MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing

‎drivers/gpu/drm/i915/intel_panel.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1699,6 +1699,8 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
16991699
if (!panel->backlight.max)
17001700
return -ENODEV;
17011701

1702+
panel->backlight.min = get_backlight_min_vbt(connector);
1703+
17021704
val = bxt_get_backlight(connector);
17031705
val = intel_panel_compute_brightness(connector, val);
17041706
panel->backlight.level = clamp(val, panel->backlight.min,
@@ -1735,6 +1737,8 @@ cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)
17351737
if (!panel->backlight.max)
17361738
return -ENODEV;
17371739

1740+
panel->backlight.min = get_backlight_min_vbt(connector);
1741+
17381742
val = bxt_get_backlight(connector);
17391743
val = intel_panel_compute_brightness(connector, val);
17401744
panel->backlight.level = clamp(val, panel->backlight.min,

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