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jbrun3tstorulf
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mmc: meson-gx: rework clk_set function
Clean-up clk_set function to prepare the next changes (DDR and clk-stop) Reviewed-by: Kevin Hilman <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
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drivers/mmc/host/meson-gx-mmc.c

Lines changed: 9 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -139,7 +139,7 @@ struct meson_host {
139139
struct clk *core_clk;
140140
struct clk_mux mux;
141141
struct clk *mux_clk;
142-
unsigned long current_clock;
142+
unsigned long req_rate;
143143

144144
struct clk_divider cfg_div;
145145
struct clk *cfg_div_clk;
@@ -275,29 +275,18 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate)
275275
int ret;
276276
u32 cfg;
277277

278-
if (clk_rate) {
279-
if (WARN_ON(clk_rate > mmc->f_max))
280-
clk_rate = mmc->f_max;
281-
else if (WARN_ON(clk_rate < mmc->f_min))
282-
clk_rate = mmc->f_min;
283-
}
284-
285-
if (clk_rate == host->current_clock)
278+
/* Same request - bail-out */
279+
if (host->req_rate == clk_rate)
286280
return 0;
287281

288282
/* stop clock */
289283
cfg = readl(host->regs + SD_EMMC_CFG);
290-
if (!(cfg & CFG_STOP_CLOCK)) {
291-
cfg |= CFG_STOP_CLOCK;
292-
writel(cfg, host->regs + SD_EMMC_CFG);
293-
}
294-
295-
dev_dbg(host->dev, "change clock rate %u -> %lu\n",
296-
mmc->actual_clock, clk_rate);
284+
cfg |= CFG_STOP_CLOCK;
285+
writel(cfg, host->regs + SD_EMMC_CFG);
286+
host->req_rate = 0;
297287

298288
if (!clk_rate) {
299289
mmc->actual_clock = 0;
300-
host->current_clock = 0;
301290
/* return with clock being stopped */
302291
return 0;
303292
}
@@ -309,13 +298,12 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate)
309298
return ret;
310299
}
311300

301+
host->req_rate = clk_rate;
312302
mmc->actual_clock = clk_get_rate(host->cfg_div_clk);
313-
host->current_clock = clk_rate;
314303

304+
dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
315305
if (clk_rate != mmc->actual_clock)
316-
dev_dbg(host->dev,
317-
"divider requested rate %lu != actual rate %u\n",
318-
clk_rate, mmc->actual_clock);
306+
dev_dbg(host->dev, "requested rate was %lu\n", clk_rate);
319307

320308
/* (re)start clock */
321309
cfg = readl(host->regs + SD_EMMC_CFG);

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