mecall backend now deals with the nested interrupt issues

Author: romancardenas

riscv-slic-macros/src/export/mecall.rs

@@ -27,7 +27,9 @@ pub fn export_quote(_input: &CodegenInput) -> TokenStream {
         #[inline]
         #[no_mangle]
         pub unsafe fn __riscv_slic_swi_pend() {
-            riscv::asm::ecall();
+            let mepc = riscv_slic::riscv::register::mepc::read();
+            riscv_slic::riscv::asm::ecall();
+            riscv_slic::riscv::register::mepc::write(mepc);
         }
 
         /// Increments the machine exception program counter by 4
@@ -38,8 +40,8 @@ pub fn export_quote(_input: &CodegenInput) -> TokenStream {
         #[inline]
         #[no_mangle]
         pub unsafe fn __riscv_slic_swi_unpend() {
-            let mepc = riscv::register::mepc::read();
-            riscv::register::mepc::write(mepc + 4);
+            let mepc = riscv_slic::riscv::register::mepc::read();
+            riscv_slic::riscv::register::mepc::write(mepc + 4);
         }
     }
 }

riscv-slic-macros/src/export/ssoft.rs

@@ -27,7 +27,7 @@ pub fn export_quote(_input: &CodegenInput) -> TokenStream {
         #[inline]
         #[no_mangle]
         pub unsafe fn __riscv_slic_swi_pend() {
-            riscv::register::sip::set_ssoft();
+            riscv_slic::riscv::register::sip::set_ssoft();
         }
 
         /// Clears the Supervisor Software Interrupt Pending bit in the `SIP` register.
@@ -38,7 +38,7 @@ pub fn export_quote(_input: &CodegenInput) -> TokenStream {
         #[inline]
         #[no_mangle]
         pub unsafe fn __riscv_slic_swi_unpend() {
-            riscv::register::sip::clear_ssoft();
+            riscv_slic::riscv::register::sip::clear_ssoft();
         }
     }
 }

riscv-slic-macros/src/swi.rs

@@ -78,7 +78,7 @@ pub fn swi_mod(input: &CodegenInput) -> TokenStream {
         ];
 
         /// The static SLIC instance
-        static mut __SLIC: MutexSLIC<#n_interrupts> = new_slic();
+        static mut __SLIC: riscv_slic::MutexSLIC<#n_interrupts> = riscv_slic::new_slic();
 
         /// Software interrupt handler to be used with the SLIC.
         #swi_handler_attribute

riscv-slic/src/api.rs

@@ -20,7 +20,7 @@ extern "Rust" {
 ///
 /// # Note
 ///
-/// This function does **NOT** modify the [`riscv::register::mstatus`] register.
+/// This function does **NOT** modify the [`mstatus`](`riscv::register::mstatus`) register.
 /// If you want to disable **ANY** other interrupt source, you must **ALSO** use the [`disable`] function.
 #[inline]
 pub fn clear_interrupts() {
@@ -38,7 +38,7 @@ pub fn clear_interrupts() {
 ///
 /// # Note
 ///
-/// This function does not modify the [`riscv::register::mstatus`] register.
+/// This function does not modify the [`mstatus`](`riscv::register::mstatus`) register.
 /// If you want to enable **ANY** other interrupt source, you must **ALSO** use the [`enable`] function.
 ///
 /// # Safety
@@ -62,9 +62,7 @@ pub fn get_threshold() -> u8 {
 ///
 /// # Safety
 ///
-/// Setting the priority threshold to a value lower than the current threshold
-/// may lead to priority inversion. If you want to make sure that the threshold
-/// is only raised, use the [`raise_threshold`] function instead.
+/// Setting the priority threshold to a value lower than the current may lead to priority inversion.
 #[inline]
 pub unsafe fn set_threshold(priority: u8) {
     __riscv_slic_set_threshold(priority);
@@ -81,20 +79,6 @@ pub unsafe fn set_priority<I: crate::InterruptNumber>(interrupt: I, priority: u8
 }
 
 /// Stabilized API for pending a software interrupt on the SLIC.
-///
-/// # Note
-///
-/// When working with the `mecall-backend` feature, special care must be taken
-/// when using this function **inside** an interrupt handler. This is because
-/// this backend uses the `ecall` instruction to trigger software interrupts.
-/// If you call this function inside an interrupt handler, the `mepc` register
-/// will be incremented by 4, leading to unexpected behavior.
-/// To avoid this, make sure that:
-///
-/// - You only call this function **outside** of interrupt handlers.
-/// - If you need to trigger a software interrupt inside an interrupt handler,
-///   do it inside a [`nested`] block. This will ensure that the
-///   `mepc` register is not incremented incorrectly.
 #[inline]
 pub fn pend<I: crate::InterruptNumber>(interrupt: I) {
     // SAFETY: it is safe to pend a software interrupt

riscv-slic/src/slic.rs

@@ -2,8 +2,11 @@ use core::cell::RefCell;
 use critical_section::Mutex;
 use heapless::binary_heap::{BinaryHeap, Max};
 
+#[doc(hidden)]
 pub type MutexSLIC<const N: usize> = Mutex<RefCell<SLIC<N>>>;
 
+#[doc(hidden)]
+#[inline]
 pub const fn new_slic<const N: usize>() -> MutexSLIC<N> {
     Mutex::new(RefCell::new(SLIC::new()))
 }