[RISCV] Add test cases for missed opportunites to treat a zext nneg as sext. NFC

These tests have a dominating icmp that require an i16 value to be
sign extended to do the compare. Because of this, the i16 will be
exported from the first basic block sign extended to XLen. We can
use this fact to remove the zext nneg in the scond block.

Author: topperc

llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

@@ -750,3 +750,90 @@ define i64 @dec_of_zexted_cmp_i64(i64 %x) {
   %dec = sub i64 %zext, 1
   ret i64 %dec
 }
+
+define void @zext_nneg_dominating_icmp_i64(i16 signext %0) {
+; RV32I-LABEL: zext_nneg_dominating_icmp_i64:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    bltz a0, .LBB46_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    slli a0, a0, 16
+; RV32I-NEXT:    srli a0, a0, 16
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    tail bar_i64
+; RV32I-NEXT:  .LBB46_2:
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: zext_nneg_dominating_icmp_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    bltz a0, .LBB46_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    srli a0, a0, 48
+; RV64I-NEXT:    tail bar_i64
+; RV64I-NEXT:  .LBB46_2:
+; RV64I-NEXT:    ret
+;
+; RV64ZBB-LABEL: zext_nneg_dominating_icmp_i64:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    bltz a0, .LBB46_2
+; RV64ZBB-NEXT:  # %bb.1:
+; RV64ZBB-NEXT:    zext.h a0, a0
+; RV64ZBB-NEXT:    tail bar_i64
+; RV64ZBB-NEXT:  .LBB46_2:
+; RV64ZBB-NEXT:    ret
+  %2 = icmp sgt i16 %0, -1
+  br i1 %2, label %3, label %5
+
+3:
+  %4 = zext nneg i16 %0 to i64
+  tail call void @bar_i64(i64 %4)
+  br label %5
+
+5:
+  ret void
+}
+
+declare void @bar_i64(i64)
+
+define void @zext_nneg_dominating_icmp_i32(i16 signext %0) {
+; RV32I-LABEL: zext_nneg_dominating_icmp_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    bltz a0, .LBB47_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    slli a0, a0, 16
+; RV32I-NEXT:    srli a0, a0, 16
+; RV32I-NEXT:    tail bar_i32
+; RV32I-NEXT:  .LBB47_2:
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: zext_nneg_dominating_icmp_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    bltz a0, .LBB47_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    srli a0, a0, 48
+; RV64I-NEXT:    tail bar_i32
+; RV64I-NEXT:  .LBB47_2:
+; RV64I-NEXT:    ret
+;
+; RV64ZBB-LABEL: zext_nneg_dominating_icmp_i32:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    bltz a0, .LBB47_2
+; RV64ZBB-NEXT:  # %bb.1:
+; RV64ZBB-NEXT:    zext.h a0, a0
+; RV64ZBB-NEXT:    tail bar_i32
+; RV64ZBB-NEXT:  .LBB47_2:
+; RV64ZBB-NEXT:    ret
+  %2 = icmp sgt i16 %0, -1
+  br i1 %2, label %3, label %5
+
+3:
+  %4 = zext nneg i16 %0 to i32
+  tail call void @bar_i32(i32 %4)
+  br label %5
+
+5:
+  ret void
+}
+
+declare void @bar_i32(i32)