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bump esp32c3 pac (#878)
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2 files changed

+17
-17
lines changed

2 files changed

+17
-17
lines changed

rtic/Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ features = ["rtic-macros/test-template"]
3131
name = "rtic"
3232

3333
[dependencies]
34-
esp32c3 = { version = "0.17.0", optional = true}
34+
esp32c3 = { version = "0.20.0", optional = true}
3535
riscv = {version = "0.10.1", optional = true}
3636
cortex-m = { version = "0.7.0", optional = true }
3737
bare-metal = "1.0.0"

rtic/src/export/riscv_esp32c3.rs

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -15,14 +15,14 @@ where
1515
f();
1616
unsafe {
1717
(*INTERRUPT_CORE0::ptr())
18-
.cpu_int_thresh
18+
.cpu_int_thresh()
1919
.write(|w| w.cpu_int_thresh().bits(1));
2020
}
2121
} else {
2222
//read current thresh
2323
let initial = unsafe {
2424
(*INTERRUPT_CORE0::ptr())
25-
.cpu_int_thresh
25+
.cpu_int_thresh()
2626
.read()
2727
.cpu_int_thresh()
2828
.bits()
@@ -31,7 +31,7 @@ where
3131
//write back old thresh
3232
unsafe {
3333
(*INTERRUPT_CORE0::ptr())
34-
.cpu_int_thresh
34+
.cpu_int_thresh()
3535
.write(|w| w.cpu_int_thresh().bits(initial));
3636
}
3737
}
@@ -62,21 +62,21 @@ pub unsafe fn lock<T, R>(ptr: *mut T, ceiling: u8, f: impl FnOnce(&mut T) -> R)
6262
} else {
6363
let current = unsafe {
6464
(*INTERRUPT_CORE0::ptr())
65-
.cpu_int_thresh
65+
.cpu_int_thresh()
6666
.read()
6767
.cpu_int_thresh()
6868
.bits()
6969
};
7070

7171
unsafe {
7272
(*INTERRUPT_CORE0::ptr())
73-
.cpu_int_thresh
73+
.cpu_int_thresh()
7474
.write(|w| w.cpu_int_thresh().bits(ceiling + 1))
7575
} //esp32c3 lets interrupts with prio equal to threshold through so we up it by one
7676
let r = f(&mut *ptr);
7777
unsafe {
7878
(*INTERRUPT_CORE0::ptr())
79-
.cpu_int_thresh
79+
.cpu_int_thresh()
8080
.write(|w| w.cpu_int_thresh().bits(current))
8181
}
8282
r
@@ -91,19 +91,19 @@ pub fn pend(int: Interrupt) {
9191
match int {
9292
Interrupt::FROM_CPU_INTR0 => peripherals
9393
.SYSTEM
94-
.cpu_intr_from_cpu_0
94+
.cpu_intr_from_cpu_0()
9595
.write(|w| w.cpu_intr_from_cpu_0().bit(true)),
9696
Interrupt::FROM_CPU_INTR1 => peripherals
9797
.SYSTEM
98-
.cpu_intr_from_cpu_1
98+
.cpu_intr_from_cpu_1()
9999
.write(|w| w.cpu_intr_from_cpu_1().bit(true)),
100100
Interrupt::FROM_CPU_INTR2 => peripherals
101101
.SYSTEM
102-
.cpu_intr_from_cpu_2
102+
.cpu_intr_from_cpu_2()
103103
.write(|w| w.cpu_intr_from_cpu_2().bit(true)),
104104
Interrupt::FROM_CPU_INTR3 => peripherals
105105
.SYSTEM
106-
.cpu_intr_from_cpu_3
106+
.cpu_intr_from_cpu_3()
107107
.write(|w| w.cpu_intr_from_cpu_3().bit(true)),
108108
_ => panic!("Unsupported software interrupt"), //should never happen, checked at compile time
109109
}
@@ -117,19 +117,19 @@ pub fn unpend(int: Interrupt) {
117117
match int {
118118
Interrupt::FROM_CPU_INTR0 => peripherals
119119
.SYSTEM
120-
.cpu_intr_from_cpu_0
120+
.cpu_intr_from_cpu_0()
121121
.write(|w| w.cpu_intr_from_cpu_0().bit(false)),
122122
Interrupt::FROM_CPU_INTR1 => peripherals
123123
.SYSTEM
124-
.cpu_intr_from_cpu_1
124+
.cpu_intr_from_cpu_1()
125125
.write(|w| w.cpu_intr_from_cpu_1().bit(false)),
126126
Interrupt::FROM_CPU_INTR2 => peripherals
127127
.SYSTEM
128-
.cpu_intr_from_cpu_2
128+
.cpu_intr_from_cpu_2()
129129
.write(|w| w.cpu_intr_from_cpu_2().bit(false)),
130130
Interrupt::FROM_CPU_INTR3 => peripherals
131131
.SYSTEM
132-
.cpu_intr_from_cpu_3
132+
.cpu_intr_from_cpu_3()
133133
.write(|w| w.cpu_intr_from_cpu_3().bit(false)),
134134
_ => panic!("Unsupported software interrupt"),
135135
}
@@ -152,10 +152,10 @@ pub fn enable(int: Interrupt, prio: u8, cpu_int_id: u8) {
152152
.write_volatile(cpu_interrupt_number as u32);
153153
//map peripheral interrupt to CPU interrupt
154154
(*INTERRUPT_CORE0::ptr())
155-
.cpu_int_enable
155+
.cpu_int_enable()
156156
.modify(|r, w| w.bits((1 << cpu_interrupt_number) | r.bits())); //enable the CPU interupt.
157157
let intr = INTERRUPT_CORE0::ptr();
158-
let intr_prio_base = (*intr).cpu_int_pri_0.as_ptr();
158+
let intr_prio_base = (*intr).cpu_int_pri_0().as_ptr();
159159

160160
intr_prio_base
161161
.offset(cpu_interrupt_number)

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