Move isa property to a field of processor_t, not sim_t

This incidentally makes it easier to support heterogeneous-hart configs
in the future

Author: jerryz123

riscv/dts.cc

@@ -14,7 +14,6 @@
 
 std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz,
                      const cfg_t* cfg,
-                     const isa_parser_t* isa,
                      std::vector<std::pair<reg_t, abstract_mem_t*>> mems,
                      std::string device_nodes)
 {
@@ -23,6 +22,7 @@ std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz,
   const char* bootargs = cfg->bootargs;
   reg_t pmpregions = cfg->pmpregions;
   reg_t pmpgranularity = cfg->pmpgranularity;
+  isa_parser_t isa(cfg->isa, cfg->priv);
 
   std::stringstream s;
   s << std::dec <<
@@ -63,8 +63,8 @@ std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz,
          "      reg = <" << cfg->hartids[i] << ">;\n"
          "      status = \"okay\";\n"
          "      compatible = \"riscv\";\n"
-         "      riscv,isa = \"" << isa->get_isa_string() << "\";\n"
-         "      mmu-type = \"riscv," << (isa->get_max_xlen() <= 32 ? "sv32" : "sv57") << "\";\n"
+         "      riscv,isa = \"" << isa.get_isa_string() << "\";\n"
+         "      mmu-type = \"riscv," << (isa.get_max_xlen() <= 32 ? "sv32" : "sv57") << "\";\n"
          "      riscv,pmpregions = <" << pmpregions << ">;\n"
          "      riscv,pmpgranularity = <" << pmpgranularity << ">;\n"
          "      clock-frequency = <" << cpu_hz << ">;\n"

riscv/dts.h

@@ -8,7 +8,6 @@
 
 std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz,
                      const cfg_t* cfg,
-                     const isa_parser_t* isa,
                      std::vector<std::pair<reg_t, abstract_mem_t*>> mems,
                      std::string device_nodes);
 

riscv/processor.cc

@@ -30,49 +30,50 @@
 #undef STATE
 #define STATE state
 
-processor_t::processor_t(const isa_parser_t *isa, const cfg_t *cfg,
+processor_t::processor_t(const char* isa_str, const char* priv_str,
+                         const cfg_t *cfg,
                          simif_t* sim, uint32_t id, bool halt_on_reset,
                          FILE* log_file, std::ostream& sout_)
-  : debug(false), halt_request(HR_NONE), isa(isa), cfg(cfg), sim(sim), id(id), xlen(0),
+: debug(false), halt_request(HR_NONE), isa(isa_str, priv_str), cfg(cfg), sim(sim), id(id), xlen(0),
   histogram_enabled(false), log_commits_enabled(false),
   log_file(log_file), sout_(sout_.rdbuf()), halt_on_reset(halt_on_reset),
   in_wfi(false), check_triggers_icount(false),
-  impl_table(256, false), extension_enable_table(isa->get_extension_table()),
+  impl_table(256, false), extension_enable_table(isa.get_extension_table()),
   last_pc(1), executions(1), TM(cfg->trigger_count)
 {
   VU.p = this;
   TM.proc = this;
 
 #ifndef HAVE_INT128
-  if (isa->has_any_vector()) {
+  if (isa.has_any_vector()) {
     fprintf(stderr, "V extension is not supported on platforms without __int128 type\n");
     abort();
   }
 
-  if (isa->extension_enabled(EXT_ZACAS) && isa->get_max_xlen() == 64) {
+  if (isa.extension_enabled(EXT_ZACAS) && isa.get_max_xlen() == 64) {
     fprintf(stderr, "Zacas extension is not supported on 64-bit platforms without __int128 type\n");
     abort();
   }
 #endif
 
-  VU.VLEN = isa->get_vlen();
-  VU.ELEN = isa->get_elen();
-  VU.vlenb = isa->get_vlen() / 8;
+  VU.VLEN = isa.get_vlen();
+  VU.ELEN = isa.get_elen();
+  VU.vlenb = isa.get_vlen() / 8;
   VU.vstart_alu = 0;
 
   register_base_instructions();
   mmu = new mmu_t(sim, cfg->endianness, this);
 
-  disassembler = new disassembler_t(isa);
-  for (auto e : isa->get_extensions())
+  disassembler = new disassembler_t(&isa);
+  for (auto e : isa.get_extensions())
     register_extension(find_extension(e.c_str())());
 
   set_pmp_granularity(cfg->pmpgranularity);
   set_pmp_num(cfg->pmpregions);
 
-  if (isa->get_max_xlen() == 32)
+  if (isa.get_max_xlen() == 32)
     set_mmu_capability(IMPL_MMU_SV32);
-  else if (isa->get_max_xlen() == 64)
+  else if (isa.get_max_xlen() == 64)
     set_mmu_capability(IMPL_MMU_SV57);
 
   set_impl(IMPL_MMU_ASID, true);
@@ -575,8 +576,8 @@ void processor_t::enable_log_commits()
 
 void processor_t::reset()
 {
-  xlen = isa->get_max_xlen();
-  state.reset(this, isa->get_max_isa());
+  xlen = isa.get_max_xlen();
+  state.reset(this, isa.get_max_isa());
   state.dcsr->halt = halt_on_reset;
   halt_on_reset = false;
   if (any_vector_extensions())
@@ -724,7 +725,7 @@ void processor_t::take_interrupt(reg_t pending_interrupts)
       abort();
 
     if (check_triggers_icount) TM.detect_icount_match();
-    throw trap_t(((reg_t)1 << (isa->get_max_xlen() - 1)) | ctz(enabled_interrupts));
+    throw trap_t(((reg_t)1 << (isa.get_max_xlen() - 1)) | ctz(enabled_interrupts));
   }
 }
 
@@ -796,7 +797,7 @@ void processor_t::debug_output_log(std::stringstream *s)
 
 void processor_t::take_trap(trap_t& t, reg_t epc)
 {
-  unsigned max_xlen = isa->get_max_xlen();
+  unsigned max_xlen = isa.get_max_xlen();
 
   if (debug) {
     std::stringstream s; // first put everything in a string, later send it to output
@@ -974,7 +975,7 @@ void processor_t::disasm(insn_t insn)
         << ": Executed " << executions << " times" << std::endl;
     }
 
-    unsigned max_xlen = isa->get_max_xlen();
+    unsigned max_xlen = isa.get_max_xlen();
 
     s << "core " << std::dec << std::setfill(' ') << std::setw(3) << id
       << std::hex << ": 0x" << std::setfill('0') << std::setw(max_xlen / 4)
@@ -993,7 +994,7 @@ void processor_t::disasm(insn_t insn)
 
 int processor_t::paddr_bits()
 {
-  unsigned max_xlen = isa->get_max_xlen();
+  unsigned max_xlen = isa.get_max_xlen();
   assert(xlen == max_xlen);
   return max_xlen == 64 ? 50 : 34;
 }
@@ -1120,7 +1121,7 @@ void processor_t::register_base_instructions()
   // add overlapping instructions first, in order
   #define DECLARE_OVERLAP_INSN(name, ext) \
     name##_overlapping = true; \
-    if (isa->extension_enabled(ext)) \
+    if (isa.extension_enabled(ext)) \
       register_base_insn((insn_desc_t) { \
         name##_match, \
         name##_mask, \

riscv/processor.h

@@ -236,12 +236,13 @@ class opcode_cache_entry_t {
 class processor_t : public abstract_device_t
 {
 public:
-  processor_t(const isa_parser_t *isa, const cfg_t* cfg,
+  processor_t(const char* isa_str, const char* priv_str,
+              const cfg_t* cfg,
               simif_t* sim, uint32_t id, bool halt_on_reset,
               FILE *log_file, std::ostream& sout_); // because of command line option --log and -s we need both
   ~processor_t();
 
-  const isa_parser_t &get_isa() { return *isa; }
+  const isa_parser_t &get_isa() { return isa; }
   const cfg_t &get_cfg() { return *cfg; }
 
   void set_debug(bool value);
@@ -303,7 +304,7 @@ class processor_t : public abstract_device_t
   void set_extension_enable(unsigned char ext, bool enable) {
     assert(!extension_assumed_const[ext]);
     extension_dynamic[ext] = true;
-    extension_enable_table[ext] = enable && isa->extension_enabled(ext);
+    extension_enable_table[ext] = enable && isa.extension_enabled(ext);
   }
   void set_impl(uint8_t impl, bool val) { impl_table[impl] = val; }
   bool supports_impl(uint8_t impl) const {
@@ -362,7 +363,7 @@ class processor_t : public abstract_device_t
   void check_if_lpad_required();
 
 private:
-  const isa_parser_t * const isa;
+  const isa_parser_t isa;
   const cfg_t * const cfg;
 
   simif_t* sim;

riscv/sim.cc

@@ -46,7 +46,6 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
              bool socket_enabled,
              FILE *cmd_file) // needed for command line option --cmd
   : htif_t(args),
-    isa(cfg->isa, cfg->priv),
     cfg(cfg),
     mems(mems),
     procs(std::max(cfg->nprocs(), size_t(1))),
@@ -99,7 +98,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
   debug_mmu = new mmu_t(this, cfg->endianness, NULL);
 
   for (size_t i = 0; i < cfg->nprocs(); i++) {
-    procs[i] = new processor_t(&isa, cfg, this, cfg->hartids[i], halted,
+    procs[i] = new processor_t(cfg->isa, cfg->priv,
+                               cfg, this, cfg->hartids[i], halted,
                                log_file.get(), sout_);
     harts[cfg->hartids[i]] = procs[i];
   }
@@ -141,7 +141,7 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
       const std::vector<std::string>& sargs = factory_sargs.second;
       device_nodes.append(factory->generate_dts(this, sargs));
     }
-    dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ, cfg, &isa, mems, device_nodes);
+    dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ, cfg, mems, device_nodes);
     dtb = dts_compile(dts);
   }
 
@@ -253,7 +253,7 @@ int sim_t::run()
   if (!debug && log)
     set_procs_debug(true);
 
-  htif_t::set_expected_xlen(isa.get_max_xlen());
+  htif_t::set_expected_xlen(harts[0]->get_isa().get_max_xlen());
 
   // htif_t::run() will repeatedly call back into sim_t::idle(), each
   // invocation of which will advance target time

riscv/sim.h

@@ -69,7 +69,6 @@ class sim_t : public htif_t, public simif_t
   static const size_t CPU_HZ = 1000000000; // 1GHz CPU
 
 private:
-  isa_parser_t isa;
   const cfg_t * const cfg;
   std::vector<std::pair<reg_t, abstract_mem_t*>> mems;
   std::vector<processor_t*> procs;

spike_main/spike-log-parser.cc

@@ -31,7 +31,7 @@ int main(int UNUSED argc, char** argv)
   cfg_t cfg;
 
   isa_parser_t isa(isa_string, DEFAULT_PRIV);
-  processor_t p(&isa, &cfg, 0, 0, false, nullptr, cerr);
+  processor_t p(isa_string, DEFAULT_PRIV, &cfg, 0, 0, false, nullptr, cerr);
   if (extension) {
     p.register_extension(extension());
   }