Skip to content

Commit 5490b75

Browse files
thejpsterthejpster
committed
Rationalise our Base Address Registers.
Treat all BARs as u32 values - the user can cast to a pointer if they wish. Resolves issues with serialising values containing pointers.
1 parent 4ca6091 commit 5490b75

File tree

16 files changed

+59
-60
lines changed

16 files changed

+59
-60
lines changed

‎aarch32-cpu/src/pmsav7.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ impl Mpu {
5656
return None;
5757
}
5858
register::Rgnr::write(register::Rgnr(idx as u32));
59-
let base = register::Irbar::read().0;
59+
let base = register::Irbar::read().0 as *mut u8;
6060
let rsr = register::Irsr::read();
6161
let racr = register::Iracr::read();
6262

@@ -85,7 +85,7 @@ impl Mpu {
8585
return None;
8686
}
8787
register::Rgnr::write(register::Rgnr(idx as u32));
88-
let base = register::Drbar::read().0;
88+
let base = register::Drbar::read().0 as *mut u8;
8989
let rsr = register::Drsr::read();
9090
let racr = register::Dracr::read();
9191

@@ -120,7 +120,7 @@ impl Mpu {
120120
if !region.size.is_aligned(region.base) {
121121
return Err(Error::UnalignedRegion(region.base));
122122
}
123-
register::Irbar::write(register::Irbar(region.base));
123+
register::Irbar::write(register::Irbar(region.base as u32));
124124
register::Irsr::write({
125125
let mut out = register::Irsr::new_with_raw_value(0);
126126
out.set_enabled(region.enabled);
@@ -145,7 +145,7 @@ impl Mpu {
145145
return Err(Error::UnalignedRegion(region.base));
146146
}
147147
register::Rgnr::write(register::Rgnr(idx as u32));
148-
register::Drbar::write(register::Drbar(region.base));
148+
register::Drbar::write(register::Drbar(region.base as u32));
149149
register::Drsr::write({
150150
let mut out = register::Drsr::new_with_raw_value(0);
151151
out.set_enabled(region.enabled);

‎aarch32-cpu/src/register/armv8r/hpfar.rs‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,26 +3,32 @@
33
use crate::register::{SysReg, SysRegRead, SysRegWrite};
44

55
/// HPFAR (*Hyp IPA Fault Address Register*)
6-
#[derive(Debug, Copy, Clone)]
6+
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
7+
#[repr(transparent)]
78
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
89
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
910
pub struct Hpfar(pub u32);
11+
1012
impl SysReg for Hpfar {
1113
const CP: u32 = 15;
1214
const CRN: u32 = 6;
1315
const OP1: u32 = 4;
1416
const CRM: u32 = 0;
1517
const OP2: u32 = 4;
1618
}
19+
1720
impl crate::register::SysRegRead for Hpfar {}
21+
1822
impl Hpfar {
1923
#[inline]
2024
/// Reads HPFAR (*Hyp IPA Fault Address Register*)
2125
pub fn read() -> Hpfar {
2226
unsafe { Self(<Self as SysRegRead>::read_raw()) }
2327
}
2428
}
29+
2530
impl crate::register::SysRegWrite for Hpfar {}
31+
2632
impl Hpfar {
2733
#[inline]
2834
/// Writes HPFAR (*Hyp IPA Fault Address Register*)

‎aarch32-cpu/src/register/armv8r/hvbar.rs‎

Lines changed: 5 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,11 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
77
/// There is no `modify` method because this register holds a single 32-bit address.
88
///
99
/// This is only available in EL2.
10-
#[derive(Clone, Copy, PartialEq, Eq)]
10+
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
1111
#[repr(transparent)]
12-
pub struct Hvbar(*mut u32);
12+
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13+
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
14+
pub struct Hvbar(pub u32);
1315

1416
impl SysReg for Hvbar {
1517
const CP: u32 = 15;
@@ -28,7 +30,7 @@ impl Hvbar {
2830
#[inline]
2931
pub fn read() -> Hvbar {
3032
// Safety: Reading this register has no side-effects and is atomic
31-
unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u32) }
33+
unsafe { Self(<Self as SysRegRead>::read_raw()) }
3234
}
3335

3436
/// Write HVBAR (*Hyp Vector Base Address Register*)
@@ -45,16 +47,3 @@ impl Hvbar {
4547
}
4648
}
4749
}
48-
49-
impl core::fmt::Debug for Hvbar {
50-
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
51-
write!(f, "HVBAR {{ {:010p} }}", self.0)
52-
}
53-
}
54-
55-
#[cfg(feature = "defmt")]
56-
impl defmt::Format for Hvbar {
57-
fn format(&self, f: defmt::Formatter) {
58-
defmt::write!(f, "HVBAR {{ 0x{=usize:08x} }}", self.0 as usize)
59-
}
60-
}

‎aarch32-cpu/src/register/armv8r/vbar.rs‎

Lines changed: 4 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
55
/// VBAR (*Vector Base Address Register*)
66
///
77
/// There is no `modify` method because this register holds a single 32-bit address.
8-
#[derive(Clone, Copy, PartialEq, Eq)]
8+
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
99
#[repr(transparent)]
10+
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1011
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
11-
pub struct Vbar(pub *mut u32);
12+
pub struct Vbar(pub u32);
1213

1314
impl SysReg for Vbar {
1415
const CP: u32 = 15;
@@ -27,7 +28,7 @@ impl Vbar {
2728
#[inline]
2829
pub fn read() -> Vbar {
2930
// Safety: Reading this register has no side-effects and is atomic
30-
unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u32) }
31+
unsafe { Self(<Self as SysRegRead>::read_raw()) }
3132
}
3233

3334
/// Write VBAR (*Vector Base Address Register*)
@@ -44,16 +45,3 @@ impl Vbar {
4445
}
4546
}
4647
}
47-
48-
impl core::fmt::Debug for Vbar {
49-
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
50-
write!(f, "VBAR {{ {:010p} }}", self.0)
51-
}
52-
}
53-
54-
#[cfg(feature = "defmt")]
55-
impl defmt::Format for Vbar {
56-
fn format(&self, f: defmt::Formatter) {
57-
defmt::write!(f, "VBAR {{ 0x{=usize:08x} }}", self.0 as usize)
58-
}
59-
}

‎aarch32-cpu/src/register/drbar.rs‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,11 @@
33
use crate::register::{SysReg, SysRegRead, SysRegWrite};
44

55
/// DRBAR (*Data Region Base Address Register*)
6-
#[derive(Debug, Copy, Clone)]
6+
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
7+
#[repr(transparent)]
78
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
8-
pub struct Drbar(pub *mut u8);
9+
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10+
pub struct Drbar(pub u32);
911

1012
impl SysReg for Drbar {
1113
const CP: u32 = 15;
@@ -14,24 +16,28 @@ impl SysReg for Drbar {
1416
const CRM: u32 = 1;
1517
const OP2: u32 = 0;
1618
}
19+
1720
impl crate::register::SysRegRead for Drbar {}
21+
1822
impl Drbar {
1923
#[inline]
2024
/// Reads DRBAR (*Data Region Base Address Register*)
2125
///
2226
/// Set RGNR to control which region this reads.
2327
pub fn read() -> Drbar {
24-
unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u8) }
28+
unsafe { Self(<Self as SysRegRead>::read_raw()) }
2529
}
2630
}
2731

2832
impl crate::register::SysRegWrite for Drbar {}
33+
2934
impl Drbar {
3035
#[inline]
3136
/// Writes DRBAR (*Data Region Base Address Register*)
3237
///
3338
/// Set RGNR to control which region this affects.
3439
pub fn write(value: Drbar) {
35-
unsafe { <Self as SysRegWrite>::write_raw(value.0 as u32) }
40+
unsafe { <Self as SysRegWrite>::write_raw(value.0) }
3641
}
3742
}
43+

‎aarch32-cpu/src/register/irbar.rs‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,34 +3,40 @@
33
use crate::register::{SysReg, SysRegRead, SysRegWrite};
44

55
/// IRBAR (*Instruction Region Base Address Register*)
6-
#[derive(Debug, Copy, Clone)]
6+
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
7+
#[repr(transparent)]
78
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
8-
pub struct Irbar(pub *mut u8);
9+
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10+
pub struct Irbar(pub u32);
11+
912
impl SysReg for Irbar {
1013
const CP: u32 = 15;
1114
const CRN: u32 = 6;
1215
const OP1: u32 = 0;
1316
const CRM: u32 = 1;
1417
const OP2: u32 = 1;
1518
}
19+
1620
impl crate::register::SysRegRead for Irbar {}
21+
1722
impl Irbar {
1823
#[inline]
1924
/// Reads IRBAR (*Instruction Region Base Address Register*)
2025
///
2126
/// Set RGNR to control which region this reads.
2227
pub fn read() -> Irbar {
23-
unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u8) }
28+
unsafe { Self(<Self as SysRegRead>::read_raw()) }
2429
}
2530
}
2631

2732
impl crate::register::SysRegWrite for Irbar {}
33+
2834
impl Irbar {
2935
#[inline]
3036
/// Writes IRBAR (*Instruction Region Base Address Register*)
3137
///
3238
/// Set RGNR to control which region this affects.
3339
pub fn write(value: Irbar) {
34-
unsafe { <Self as SysRegWrite>::write_raw(value.0 as u32) }
40+
unsafe { <Self as SysRegWrite>::write_raw(value.0) }
3541
}
3642
}

‎aarch32-cpu/src/register/rvbar.rs‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,18 +3,22 @@
33
use crate::register::{SysReg, SysRegRead};
44

55
/// RVBAR (*Reset Vector Base Address Register*)
6-
#[derive(Debug, Clone, Copy)]
6+
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
7+
#[repr(transparent)]
78
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
89
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
910
pub struct Rvbar(pub u32);
11+
1012
impl SysReg for Rvbar {
1113
const CP: u32 = 15;
1214
const CRN: u32 = 12;
1315
const OP1: u32 = 0;
1416
const CRM: u32 = 0;
1517
const OP2: u32 = 1;
1618
}
19+
1720
impl crate::register::SysRegRead for Rvbar {}
21+
1822
impl Rvbar {
1923
#[inline]
2024
/// Reads RVBAR (*Reset Vector Base Address Register*)

‎examples/mps3-an536/reference/registers-armv8r-none-eabihf.out‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xd13 rev=0x3 }
22
CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
33
IMP_CBAR { 0xf0000000 }
4-
VBAR { 0x08000000 }
4+
Vbar(8000000)
55
PMSA-v8 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }
66
Region 0: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
77
Region 1: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }

‎examples/mps3-an536/src/bin/registers.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,12 +22,12 @@ fn main() -> ! {
2222
}
2323

2424
fn chip_info() {
25-
println!("{:?}", aarch32_cpu::register::Midr::read());
26-
println!("{:?}", aarch32_cpu::register::Cpsr::read());
25+
println!("{:x?}", aarch32_cpu::register::Midr::read());
26+
println!("{:x?}", aarch32_cpu::register::Cpsr::read());
2727
#[cfg(arm_architecture = "v8-r")]
2828
{
29-
println!("{:?}", aarch32_cpu::register::ImpCbar::read());
30-
println!("{:?}", aarch32_cpu::register::Vbar::read());
29+
println!("{:x?}", aarch32_cpu::register::ImpCbar::read());
30+
println!("{:x?}", aarch32_cpu::register::Vbar::read());
3131
// This only works in EL2 and start-up put us in EL1
3232
// println!("{:?}", aarch32_cpu::register::Hvbar::read());
3333
}

‎examples/versatileab/reference/registers-armv4t-none-eabi.out‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
MIDR { implementer=0x69 variant=0x0 arch=0x5 part_no=0x210 rev=0x0 }
22
CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
3-
Mpidr(1761943808)
3+
Mpidr(69052100)
44
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
55
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after

0 commit comments

Comments
 (0)