77
88use crate :: register;
99
10- use arbitrary_int:: u3 ;
10+ use arbitrary_int:: { u2 , u3 } ;
1111#[ doc( inline) ]
1212pub use register:: drsr:: RegionSize ;
1313
@@ -347,10 +347,10 @@ impl MemAttrBits {
347347 ( 0b010 , false , false ) => Some ( MemAttr :: Device { shareable : false } ) ,
348348 ( tex, c, b) if tex >= 0b100 => {
349349 let outer = tex & 0b11 ;
350- let inner = if c { 2 } else { 0 } | if b { 1 } else { 0 } ;
350+ let inner = ( c as u8 ) << 1 | ( b as u8 ) ;
351351 Some ( MemAttr :: Cacheable {
352- outer : CacheablePolicy :: decode ( outer) ,
353- inner : CacheablePolicy :: decode ( inner) ,
352+ outer : CacheablePolicy :: new_with_raw_value ( u2 :: from_u8 ( outer) ) ,
353+ inner : CacheablePolicy :: new_with_raw_value ( u2 :: from_u8 ( inner) ) ,
354354 shareable : self . s ,
355355 } )
356356 }
@@ -363,26 +363,15 @@ impl MemAttrBits {
363363}
364364
365365/// Describes the cache policy of a region
366- #[ derive( Debug , Copy , Clone , PartialEq , Eq ) ]
367- #[ repr ( u8 ) ]
366+ #[ derive( Debug , PartialEq , Eq ) ]
367+ #[ bitbybit :: bitenum ( u2 , exhaustive = true ) ]
368368pub enum CacheablePolicy {
369369 NonCacheable = 0b00 ,
370370 WriteBackWriteAllocate = 0b01 ,
371371 WriteThroughNoWriteAllocate = 0b10 ,
372372 WriteBackNoWriteAllocate = 0b11 ,
373373}
374374
375- impl CacheablePolicy {
376- const fn decode ( input : u8 ) -> CacheablePolicy {
377- match input {
378- 0b00 => CacheablePolicy :: NonCacheable ,
379- 0b01 => CacheablePolicy :: WriteBackWriteAllocate ,
380- 0b10 => CacheablePolicy :: WriteThroughNoWriteAllocate ,
381- _ => CacheablePolicy :: WriteBackNoWriteAllocate ,
382- }
383- }
384- }
385-
386375#[ cfg( test) ]
387376mod test {
388377 use super :: * ;
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