small docs mistake

Author: robamu

cortex-ar/src/cache.rs

@@ -8,7 +8,7 @@ use crate::register::{Dccisw, Dccsw, Dcisw};
 ///
 /// - A: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
 ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
-///   4.
+///   3.
 /// - N: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
 ///   5.
 /// - S: log2(NUM OF SETS). For systems with a fixed cache size, the number of sets can be
@@ -33,7 +33,7 @@ pub fn invalidate_l1_data_cache<const A: usize, const N: usize, const S: usize>(
 ///
 /// - A: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
 ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
-///   4.
+///   3.
 /// - N: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
 ///   5.
 /// - S: log2(NUM OF SETS). For systems with a fixed cache size, the number of sets can be
@@ -58,7 +58,7 @@ pub fn clean_l1_data_cache<const A: usize, const N: usize, const S: usize>() {
 ///
 /// - A: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
 ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
-///   4.
+///   3.
 /// - N: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
 ///   5.
 /// - S: log2(NUM OF SETS). For systems with a fixed cache size, the number of sets can be

cortex-ar/src/register/dccisw.rs

@@ -13,7 +13,7 @@ impl Dccisw {
     ///
     /// - A: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
     ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
-    ///   4.
+    ///   3.
     /// - N: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
     ///   5.
     #[inline]
@@ -28,7 +28,7 @@ impl Dccisw {
     ///
     /// - a: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
     ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
-    ///   4.
+    ///   3.
     /// - n: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
     ///   5.
     #[inline]

cortex-ar/src/register/dccsw.rs

@@ -13,7 +13,7 @@ impl Dccsw {
     ///
     /// - A: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
     ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
-    ///   4.
+    ///   3.
     /// - N: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
     ///   5.
     #[inline]
@@ -28,7 +28,7 @@ impl Dccsw {
     ///
     /// - a: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
     ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
-    ///   4.
+    ///   3.
     /// - n: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
     ///   5.
     #[inline]

cortex-ar/src/register/dcisw.rs

@@ -13,7 +13,7 @@ impl Dcisw {
     ///
     /// - A: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
     ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
-    ///   4.
+    ///   3.
     /// - N: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
     ///   5.
     #[inline]
@@ -28,7 +28,7 @@ impl Dcisw {
     ///
     /// - a: log2(ASSOCIATIVITY) rounded up to the next integer if necessary. For example, a 4-way
     ///   associative cache will have a value of 2 and a 8-way associative cache will have a value of
-    ///   4.
+    ///   3.
     /// - n: log2(LINE LENGTH). For example, a 32-byte line length (4 words) will have a value of
     ///   5.
     #[inline]