Add a lot more registers.

The values are taken from the Cortex-R52 Reference Manual. We
only have basic reads/writes for the new ones - I haven't drilled
down into the bitfields.

Author: thejpster

cortex-r-examples/src/bin/gic.rs

@@ -42,7 +42,7 @@ fn dump_cpsr() {
 /// Called by [`kmain`].
 fn main() -> Result<(), core::fmt::Error> {
     // Get the GIC address by reading CBAR
-    let periphbase = cortex_r::register::Cbar::read().periphbase();
+    let periphbase = cortex_r::register::ImpCbar::read().periphbase();
     println!("Found PERIPHBASE {:010p}", periphbase);
     let gicd_base = periphbase.wrapping_byte_add(GICD_BASE_OFFSET);
     let gicr_base = periphbase.wrapping_byte_add(GICR_BASE_OFFSET);

cortex-r-examples/src/bin/registers.rs

@@ -22,7 +22,7 @@ pub extern "C" fn kmain() {
     println!("{:?}", cortex_r::register::Cpsr::read());
     #[cfg(arm_architecture = "v8-r")]
     {
-        println!("{:?}", cortex_r::register::Cbar::read());
+        println!("{:?}", cortex_r::register::ImpCbar::read());
         println!("{:?}", cortex_r::register::Vbar::read());
         // This only works in EL2 and start-up put us in EL1
         // println!("{:?}", cortex_r::register::Hvbar::read());

cortex-r/src/register/actlr.rs

@@ -0,0 +1,35 @@
+//! Code for managing ACTLR (*Auxiliary Control Register*)
+
+use crate::register::{SysReg, SysRegRead, SysRegWrite};
+
+/// ACTLR (*Auxiliary Control Register*)
+pub struct Actlr(pub u32);
+impl SysReg for Actlr {
+    const CP: u32 = 15;
+    const CRN: u32 = 1;
+    const OP1: u32 = 0;
+    const CRM: u32 = 0;
+    const OP2: u32 = 1;
+}
+impl crate::register::SysRegRead for Actlr {}
+impl Actlr {
+    #[inline]
+    /// Reads ACTLR (*Auxiliary Control Register*)
+    pub fn read() -> Actlr {
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+    }
+}
+impl crate::register::SysRegWrite for Actlr {}
+impl Actlr {
+    #[inline]
+    /// Writes ACTLR (*Auxiliary Control Register*)
+    ///
+    /// # Safety
+    ///
+    /// Ensure that this value is appropriate for this register
+    pub unsafe fn write(value: Self) {
+        unsafe {
+            <Self as SysRegWrite>::write_raw(value.0);
+        }
+    }
+}

cortex-r/src/register/actlr2.rs

@@ -0,0 +1,35 @@
+//! Code for managing ACTLR2 (*Auxiliary Control Register 2*)
+
+use crate::register::{SysReg, SysRegRead, SysRegWrite};
+
+/// ACTLR2 (*Auxiliary Control Register 2*)
+pub struct Actlr2(pub u32);
+impl SysReg for Actlr2 {
+    const CP: u32 = 15;
+    const CRN: u32 = 1;
+    const OP1: u32 = 0;
+    const CRM: u32 = 0;
+    const OP2: u32 = 3;
+}
+impl crate::register::SysRegRead for Actlr2 {}
+impl Actlr2 {
+    #[inline]
+    /// Reads ACTLR2 (*Auxiliary Control Register 2*)
+    pub fn read() -> Actlr2 {
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+    }
+}
+impl crate::register::SysRegWrite for Actlr2 {}
+impl Actlr2 {
+    #[inline]
+    /// Writes ACTLR2 (*Auxiliary Control Register 2*)
+    ///
+    /// # Safety
+    ///
+    /// Ensure that this value is appropriate for this register
+    pub unsafe fn write(value: Self) {
+        unsafe {
+            <Self as SysRegWrite>::write_raw(value.0);
+        }
+    }
+}

cortex-r/src/register/adfsr.rs

@@ -0,0 +1,35 @@
+//! Code for managing ADFSR (*Auxiliary Data Fault Status Register*)
+
+use crate::register::{SysReg, SysRegRead, SysRegWrite};
+
+/// ADFSR (*Auxiliary Data Fault Status Register*)
+pub struct Adfsr(pub u32);
+impl SysReg for Adfsr {
+    const CP: u32 = 15;
+    const CRN: u32 = 5;
+    const OP1: u32 = 0;
+    const CRM: u32 = 1;
+    const OP2: u32 = 0;
+}
+impl crate::register::SysRegRead for Adfsr {}
+impl Adfsr {
+    #[inline]
+    /// Reads ADFSR (*Auxiliary Data Fault Status Register*)
+    pub fn read() -> Adfsr {
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+    }
+}
+impl crate::register::SysRegWrite for Adfsr {}
+impl Adfsr {
+    #[inline]
+    /// Writes ADFSR (*Auxiliary Data Fault Status Register*)
+    ///
+    /// # Safety
+    ///
+    /// Ensure that this value is appropriate for this register
+    pub unsafe fn write(value: Self) {
+        unsafe {
+            <Self as SysRegWrite>::write_raw(value.0);
+        }
+    }
+}

cortex-r/src/register/aidr.rs

@@ -0,0 +1,21 @@
+//! Code for managing AIDR (*Auxiliary ID Register*)
+
+use crate::register::{SysReg, SysRegRead};
+
+/// AIDR (*Auxiliary ID Register*)
+pub struct Aidr(pub u32);
+impl SysReg for Aidr {
+    const CP: u32 = 15;
+    const CRN: u32 = 0;
+    const OP1: u32 = 1;
+    const CRM: u32 = 0;
+    const OP2: u32 = 7;
+}
+impl crate::register::SysRegRead for Aidr {}
+impl Aidr {
+    #[inline]
+    /// Reads AIDR (*Auxiliary ID Register*)
+    pub fn read() -> Aidr {
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+    }
+}

cortex-r/src/register/aifsr.rs

@@ -0,0 +1,35 @@
+//! Code for managing AIFSR (*Auxiliary Instruction Fault Status Register*)
+
+use crate::register::{SysReg, SysRegRead, SysRegWrite};
+
+/// AIFSR (*Auxiliary Instruction Fault Status Register*)
+pub struct Aifsr(pub u32);
+impl SysReg for Aifsr {
+    const CP: u32 = 15;
+    const CRN: u32 = 5;
+    const OP1: u32 = 0;
+    const CRM: u32 = 1;
+    const OP2: u32 = 1;
+}
+impl crate::register::SysRegRead for Aifsr {}
+impl Aifsr {
+    #[inline]
+    /// Reads AIFSR (*Auxiliary Instruction Fault Status Register*)
+    pub fn read() -> Aifsr {
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+    }
+}
+impl crate::register::SysRegWrite for Aifsr {}
+impl Aifsr {
+    #[inline]
+    /// Writes AIFSR (*Auxiliary Instruction Fault Status Register*)
+    ///
+    /// # Safety
+    ///
+    /// Ensure that this value is appropriate for this register
+    pub unsafe fn write(value: Self) {
+        unsafe {
+            <Self as SysRegWrite>::write_raw(value.0);
+        }
+    }
+}

cortex-r/src/register/amair0.rs

@@ -0,0 +1,35 @@
+//! Code for managing AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)
+
+use crate::register::{SysReg, SysRegRead, SysRegWrite};
+
+/// AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)
+pub struct Amair0(pub u32);
+impl SysReg for Amair0 {
+    const CP: u32 = 15;
+    const CRN: u32 = 10;
+    const OP1: u32 = 0;
+    const CRM: u32 = 3;
+    const OP2: u32 = 0;
+}
+impl crate::register::SysRegRead for Amair0 {}
+impl Amair0 {
+    #[inline]
+    /// Reads AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)
+    pub fn read() -> Amair0 {
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+    }
+}
+impl crate::register::SysRegWrite for Amair0 {}
+impl Amair0 {
+    #[inline]
+    /// Writes AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)
+    ///
+    /// # Safety
+    ///
+    /// Ensure that this value is appropriate for this register
+    pub unsafe fn write(value: Self) {
+        unsafe {
+            <Self as SysRegWrite>::write_raw(value.0);
+        }
+    }
+}

cortex-r/src/register/amair1.rs

@@ -0,0 +1,35 @@
+//! Code for managing AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)
+
+use crate::register::{SysReg, SysRegRead, SysRegWrite};
+
+/// AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)
+pub struct Amair1(pub u32);
+impl SysReg for Amair1 {
+    const CP: u32 = 15;
+    const CRN: u32 = 10;
+    const OP1: u32 = 0;
+    const CRM: u32 = 3;
+    const OP2: u32 = 1;
+}
+impl crate::register::SysRegRead for Amair1 {}
+impl Amair1 {
+    #[inline]
+    /// Reads AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)
+    pub fn read() -> Amair1 {
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+    }
+}
+impl crate::register::SysRegWrite for Amair1 {}
+impl Amair1 {
+    #[inline]
+    /// Writes AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)
+    ///
+    /// # Safety
+    ///
+    /// Ensure that this value is appropriate for this register
+    pub unsafe fn write(value: Self) {
+        unsafe {
+            <Self as SysRegWrite>::write_raw(value.0);
+        }
+    }
+}

cortex-r/src/register/armv8r/cnthctl.rs

@@ -0,0 +1,35 @@
+//! Code for managing CNTHCTL (*Counter-timer Hyp Control Register*)
+
+use crate::register::{SysReg, SysRegRead, SysRegWrite};
+
+/// CNTHCTL (*Counter-timer Hyp Control Register*)
+pub struct Cnthctl(pub u32);
+impl SysReg for Cnthctl {
+    const CP: u32 = 15;
+    const CRN: u32 = 14;
+    const OP1: u32 = 4;
+    const CRM: u32 = 1;
+    const OP2: u32 = 0;
+}
+impl crate::register::SysRegRead for Cnthctl {}
+impl Cnthctl {
+    #[inline]
+    /// Reads CNTHCTL (*Counter-timer Hyp Control Register*)
+    pub fn read() -> Cnthctl {
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+    }
+}
+impl crate::register::SysRegWrite for Cnthctl {}
+impl Cnthctl {
+    #[inline]
+    /// Writes CNTHCTL (*Counter-timer Hyp Control Register*)
+    ///
+    /// # Safety
+    ///
+    /// Ensure that this value is appropriate for this register
+    pub unsafe fn write(value: Self) {
+        unsafe {
+            <Self as SysRegWrite>::write_raw(value.0);
+        }
+    }
+}