Abstract the MCR and MRC operations.

Author: jonathanpallant

cortex-r/src/register/armv8r/cbar.rs

@@ -1,23 +1,27 @@
 //! Code for the *Configuration Base Address Register*
 
+use crate::register::{SysReg, SysRegRead};
+
 /// The *Configuration Base Address Register* (CBAR)
 #[derive(Clone, Copy, PartialEq, Eq)]
 pub struct Cbar(u32);
 
+impl SysReg for Cbar {
+    const CP: u32 = 15;
+    const CRN: u32 = 15;
+    const OP1: u32 = 1;
+    const CRM: u32 = 3;
+    const OP2: u32 = 0;
+}
+
+impl SysRegRead for Cbar {}
+
 impl Cbar {
     /// Reads the *Configuration Base Address Register*
     #[inline]
     pub fn read() -> Cbar {
-        let r: u32;
-        #[cfg(target_arch = "arm")]
-        unsafe {
-            core::arch::asm!("mrc p15, 1, {}, c15, c3, 0", out(reg) r, options(nomem, nostack, preserves_flags));
-        }
-        #[cfg(not(target_arch = "arm"))]
-        {
-            r = 0;
-        }
-        Self(r)
+        // Safety: this read has no side-effects
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 
     /// Get the periphbase address

cortex-r/src/register/armv8r/hactlr.rs

@@ -1,5 +1,7 @@
 //! Code for managing the *Hyp Auxiliary Control Register*
 
+use crate::register::{SysReg, SysRegRead, SysRegWrite};
+
 /// The *Hyp Auxiliary Control Register* (HACTRL)
 #[bitbybit::bitfield(u32)]
 pub struct Hactlr {
@@ -33,31 +35,33 @@ pub struct Hactlr {
     cpuactlr: bool,
 }
 
+impl SysReg for Hactlr {
+    const CP: u32 = 15;
+    const CRN: u32 = 1;
+    const OP1: u32 = 4;
+    const CRM: u32 = 0;
+    const OP2: u32 = 1;
+}
+
+impl SysRegRead for Hactlr {}
+
+impl SysRegWrite for Hactlr {}
+
 impl Hactlr {
     /// Reads the *Hyp Auxiliary Control Register*
     #[inline]
     pub fn read() -> Hactlr {
-        let r: u32;
         // Safety: Reading this register has no side-effects and is atomic
-        #[cfg(target_arch = "arm")]
-        unsafe {
-            core::arch::asm!("mrc p15, 4, {}, c1, c0, 1", out(reg) r, options(nomem, nostack, preserves_flags));
-        }
-        #[cfg(not(target_arch = "arm"))]
-        {
-            r = 0;
-        }
-        Self::new_with_raw_value(r)
+        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 
     /// Write to the *Hyp Auxiliary Control Register*
     #[inline]
-    pub fn write(_value: Self) {
+    pub fn write(value: Self) {
         // Safety: Writing this register is atomic
-        #[cfg(target_arch = "arm")]
         unsafe {
-            core::arch::asm!("mcr p15, 4, {}, c1, c0, 1", in(reg) _value.raw_value(), options(nomem, nostack, preserves_flags));
-        };
+            <Self as SysRegWrite>::write_raw(value.raw_value());
+        }
     }
 
     /// Modify the *Hyp Auxiliary Control Register*

cortex-r/src/register/armv8r/hvbar.rs

@@ -1,5 +1,7 @@
 //! Code for the *Hyp Vector Base Address Register*
 
+use crate::register::{SysReg, SysRegRead, SysRegWrite};
+
 /// The *Hyp Vector Base Address Register* (Hvbar)
 ///
 /// There is no `modify` method because this register holds a single 32-bit address.
@@ -9,22 +11,24 @@
 #[repr(transparent)]
 pub struct Hvbar(*mut u32);
 
+impl SysReg for Hvbar {
+    const CP: u32 = 15;
+    const CRN: u32 = 12;
+    const OP1: u32 = 4;
+    const CRM: u32 = 0;
+    const OP2: u32 = 0;
+}
+
+impl SysRegRead for Hvbar {}
+
+impl SysRegWrite for Hvbar {}
+
 impl Hvbar {
     /// Reads the *Hyp Vector Base Address Register*
-    ///
-    /// Will cause an exception unless you are in EL2.
     #[inline]
     pub fn read() -> Hvbar {
-        let r: usize;
-        #[cfg(target_arch = "arm")]
-        unsafe {
-            core::arch::asm!("mrc p15, 4, {}, c12, c0, 0", out(reg) r, options(nomem, nostack, preserves_flags));
-        }
-        #[cfg(not(target_arch = "arm"))]
-        {
-            r = 0;
-        }
-        Self(r as *mut u32)
+        // Safety: Reading this register has no side-effects and is atomic
+        unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u32) }
     }
 
     /// Write to the *Hyp Vector Base Address Register*
@@ -34,12 +38,11 @@ impl Hvbar {
     /// You must supply a correctly-aligned address of a valid Arm Cortex-R
     /// Vector Table.
     #[inline]
-    pub fn write(_value: Self) {
+    pub unsafe fn write(value: Self) {
         // Safety: Writing this register is atomic
-        #[cfg(target_arch = "arm")]
         unsafe {
-            core::arch::asm!("mcr p15, 0, {}, c12, c0, 0", in(reg) _value.0, options(nomem, nostack, preserves_flags));
-        };
+            <Self as SysRegWrite>::write_raw(value.0 as u32);
+        }
     }
 }
 

cortex-r/src/register/armv8r/vbar.rs

@@ -1,26 +1,32 @@
 //! Code for the *Vector Base Address Register*
 
+use crate::register::{SysReg, SysRegRead, SysRegWrite};
+
 /// The *Vector Base Address Register* (VBAR)
 ///
 /// There is no `modify` method because this register holds a single 32-bit address.
 #[derive(Clone, Copy, PartialEq, Eq)]
 #[repr(transparent)]
 pub struct Vbar(pub *mut u32);
 
+impl SysReg for Vbar {
+    const CP: u32 = 15;
+    const CRN: u32 = 12;
+    const OP1: u32 = 0;
+    const CRM: u32 = 0;
+    const OP2: u32 = 0;
+}
+
+impl SysRegRead for Vbar {}
+
+impl SysRegWrite for Vbar {}
+
 impl Vbar {
     /// Reads the *Vector Base Address Register*
     #[inline]
     pub fn read() -> Vbar {
-        let r: usize;
-        #[cfg(target_arch = "arm")]
-        unsafe {
-            core::arch::asm!("mrc p15, 0, {}, c12, c0, 0", out(reg) r, options(nomem, nostack, preserves_flags));
-        }
-        #[cfg(not(target_arch = "arm"))]
-        {
-            r = 0;
-        }
-        Self(r as *mut u32)
+        // Safety: Reading this register has no side-effects and is atomic
+        unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u32) }
     }
 
     /// Write to the *Vector Base Address Register*
@@ -30,12 +36,11 @@ impl Vbar {
     /// You must supply a correctly-aligned address of a valid Arm Cortex-R
     /// Vector Table.
     #[inline]
-    pub unsafe fn write(_value: Self) {
+    pub unsafe fn write(value: Self) {
         // Safety: Writing this register is atomic
-        #[cfg(target_arch = "arm")]
         unsafe {
-            core::arch::asm!("mcr p15, 0, {}, c12, c0, 0", in(reg) _value.0, options(nomem, nostack, preserves_flags));
-        };
+            <Self as SysRegWrite>::write_raw(value.0 as u32);
+        }
     }
 }
 

cortex-r/src/register/midr.rs

@@ -2,6 +2,8 @@
 
 use arbitrary_int::{u12, u4};
 
+use super::{SysReg, SysRegRead};
+
 /// The *Main ID Register* (MIDR)
 #[bitbybit::bitfield(u32)]
 pub struct Midr {
@@ -22,21 +24,22 @@ pub struct Midr {
     rev: u4,
 }
 
+impl SysReg for Midr {
+    const CP: u32 = 15;
+    const CRN: u32 = 0;
+    const OP1: u32 = 0;
+    const CRM: u32 = 0;
+    const OP2: u32 = 0;
+}
+
+impl SysRegRead for Midr {}
+
 impl Midr {
     /// Reads the *Main ID Register*
     #[inline]
     pub fn read() -> Midr {
-        let r: u32;
         // Safety: Reading this register has no side-effects and is atomic
-        #[cfg(target_arch = "arm")]
-        unsafe {
-            core::arch::asm!("mrc p15, 0, {}, c0, c0, 0", out(reg) r, options(nomem, nostack, preserves_flags));
-        }
-        #[cfg(not(target_arch = "arm"))]
-        {
-            r = 0;
-        }
-        Self::new_with_raw_value(r)
+        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 

cortex-r/src/register/mod.rs

@@ -18,6 +18,66 @@ mod armv8r;
 #[cfg(arm_architecture = "v8-r")]
 pub use armv8r::*;
 
+/// Describes a System Register
+trait SysReg {
+    /// Which Co-Processor (e.g. 15 for CP15) is this register in?
+    const CP: u32;
+    /// Which CRn argument (e.g. 0 for c0) accesses this register
+    const CRN: u32;
+    /// Which OP1 argument accesses this register
+    const OP1: u32;
+    /// Which CRm argument (e.g. 0 for c0) accesses this register
+    const CRM: u32;
+    /// Which OP2 argument accesses this register
+    const OP2: u32;
+}
+
+/// Readable System Registers
+trait SysRegRead: SysReg {
+    #[inline]
+    unsafe fn read_raw() -> u32 {
+        let r: u32;
+        #[cfg(target_arch = "arm")]
+        unsafe {
+            core::arch::asm!(
+                "mrc p{cp}, {op1}, {reg}, c{crn}, c{crm}, {op2}",
+                cp = const Self::CP,
+                op1 = const Self::OP1,
+                reg = out(reg) r,
+                crn = const Self::CRN,
+                crm = const Self::CRM,
+                op2 = const Self::OP2,
+                options(nomem, nostack, preserves_flags)
+            );
+        }
+        #[cfg(not(target_arch = "arm"))]
+        {
+            r = 0;
+        }
+        r
+    }
+}
+
+/// Writable System Registers
+trait SysRegWrite: SysReg {
+    #[inline]
+    unsafe fn write_raw(_value: u32) {
+        #[cfg(target_arch = "arm")]
+        unsafe {
+            core::arch::asm!(
+                "mcr p{cp}, {op1}, {reg}, c{crn}, c{crm}, {op2}",
+                cp = const Self::CP,
+                op1 = const Self::OP1,
+                reg = in(reg) _value,
+                crn = const Self::CRN,
+                crm = const Self::CRM,
+                op2 = const Self::OP2,
+                options(nomem, nostack, preserves_flags)
+            );
+        }
+    }
+}
+
 // TODO:
 
 // Multiprocessor Affinity Register (MPIDR)

cortex-r/src/register/sctlr.rs

@@ -1,5 +1,7 @@
 //! Code for managing the *System Control Register*
 
+use super::{SysReg, SysRegRead, SysRegWrite};
+
 /// The *System Control Register* (SCTLR)
 #[bitbybit::bitfield(u32)]
 pub struct Sctlr {
@@ -53,31 +55,32 @@ pub struct Sctlr {
     m: bool,
 }
 
+impl SysReg for Sctlr {
+    const CP: u32 = 15;
+    const CRN: u32 = 1;
+    const OP1: u32 = 0;
+    const CRM: u32 = 0;
+    const OP2: u32 = 0;
+}
+
+impl SysRegRead for Sctlr {}
+
+impl SysRegWrite for Sctlr {}
+
 impl Sctlr {
     /// Reads the *System Control Register*
     #[inline]
     pub fn read() -> Self {
-        let r: u32;
-        // Safety: Reading this register has no side-effects and is atomic
-        #[cfg(target_arch = "arm")]
-        unsafe {
-            core::arch::asm!("mrc p15, 0, {}, c1, c0, 0", out(reg) r, options(nomem, nostack, preserves_flags));
-        }
-        #[cfg(not(target_arch = "arm"))]
-        {
-            r = 0;
-        }
-        Self::new_with_raw_value(r)
+        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 
     /// Write to the *System Control Register*
     #[inline]
     pub fn write(_value: Self) {
         // Safety: Writing this register is atomic
-        #[cfg(target_arch = "arm")]
         unsafe {
-            core::arch::asm!("mcr p15, 0, {}, c1, c0, 0", in(reg) _value.raw_value(), options(nomem, nostack, preserves_flags));
-        };
+            <Self as SysRegWrite>::write_raw(_value.raw_value());
+        }
     }
 
     /// Modify the *System Control Register*