update MMU code

Author: robamu

cortex-ar/CHANGELOG.md

@@ -13,6 +13,13 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - API for inner cache maintenance as part of the new `cache` module. This includes functions to
   completely clean, invalidate or clean & invalidate the L1 data cache or perform data cache
   maintenance by MVA (specific address).
+- Added new  `L1Section::set_section_attrs` and `L1Section::section_attrs` method. Also added
+  low-level `L1Section::new_with_addr_upper_bits_and_attrs` constructor.
+
+### Changed
+
+- MMU code: Use more `arbitrary-int` types for MMU configuration bits.
+- Renamed `L1Section::new` to `L1Section::new_with_addr_and_attrs`.
 
 ## [v0.2.0]
 

cortex-ar/Cargo.toml

@@ -29,6 +29,7 @@ arbitrary-int = "1.3.0"
 bitbybit = "1.3.3"
 num_enum = { version = "0.7", default-features = false }
 critical-section = {version = "1.2.0", features = ["restore-state-u8"], optional = true}
+thiserror = { version = "2", default-features = false }
 defmt = {version = "0.3", optional = true}
 
 [build-dependencies]
@@ -42,7 +43,7 @@ critical-section-single-core = ["critical-section"]
 # a CAS spinlock.
 critical-section-multi-core = ["critical-section"]
 # Adds defmt::Format implementation for the register types
-defmt = ["dep:defmt"]
+defmt = ["dep:defmt", "arbitrary-int/defmt"]
 
 [package.metadata.docs.rs]
 targets = ["armv7r-none-eabihf", "armv7r-none-eabi", "armv7a-none-eabihf"]