Merge pull request #29 from rust-embedded/switch_to_tock_registers

Switch from register-rs to tock-registers

Author: andre-richter

.editorconfig

@@ -0,0 +1,25 @@
+# editorconfig.org
+
+root = true
+
+[*]
+charset = utf-8
+end_of_line = lf
+insert_final_newline = true
+indent_style = space
+trim_trailing_whitespace = true
+max_line_length = 100
+
+[Makefile]
+indent_style = tab
+indent_size = 8
+
+[*.rs]
+indent_size = 4
+
+[*.s]
+indent_style = tab
+indent_size = 8
+
+[*.toml]
+indent_size = 4

.vscode/settings.json

@@ -3,8 +3,8 @@
     "editor.rulers": [
         100
     ],
-    "rust-analyzer.checkOnSave.extraArgs": [
-        "--target=aarch64-unknown-none-softfloat"
-    ],
-    "rust-analyzer.checkOnSave.allTargets": false
-}
+    "rust-analyzer.checkOnSave.allTargets": false,
+    "rust-analyzer.cargo.target": "aarch64-unknown-none-softfloat",
+    "rust-analyzer.lens.debug": false,
+    "rust-analyzer.lens.run": false
+}

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "cortex-a"
-version = "5.1.6"
+version = "6.0.0"
 authors = ["Andre Richter <[email protected]>"]
 description = "Low level access to Cortex-A processors"
 homepage = "https://github.com/rust-embedded/cortex-a"
@@ -11,8 +11,13 @@ categories = ["embedded", "hardware-support", "no-std"]
 license = "MIT/Apache-2.0"
 edition = "2018"
 exclude = [
+        ".github",
+        ".gitignore",
+        ".rustfmt.toml",
+        ".vscode",
+        ".editorconfig",
         "Makefile"
 ]
 
 [dependencies]
-register = "1.x.x"
+tock-registers = { version = "0.7.x", default-features = false } # Use it as interface-only library.

Makefile

@@ -8,10 +8,6 @@ clippy:
 	cargo clippy --target $(TARGET)
 	cargo clippy
 
-check:
-	cargo check --target $(TARGET)
-	cargo check
-
 fmt:
 	cargo fmt
 

README.md

@@ -5,21 +5,53 @@
 
 Low level access to Cortex-A processors.
 
-## Currently Supported Architectures
+## Currently Supported Execution States
 
 - [x] AArch64
 - [ ] AArch32
 
 ## Minimum Supported Rust Version
 
-Requires rustc 1.45.0 or later due to use of the new `asm!()` syntax.
+Requires a recent nightly of Rust.
 
 ## Usage
 
-Example from https://github.com/rust-embedded/rust-raspi3-OS-tutorials
+Please note that for using this crate's [register definitions](src/registers) (as provided by
+`cortex_a::registers::*`), you need to also include
+[`tock-registers`](https://crates.io/crates/tock-registers) in your project. This is because the
+`interface` traits provided by `tock-registers` are implemented by this crate. You should include
+the same version of `tock-registers` as is being used by this crate to ensure sane
+interoperatbility.
+
+For example, in the following snippet, `X.Y.Z` should be the same version of `tock-registers` that
+is mentioned in `cortex-a`'s [`Cargo.toml`](Cargo.toml).
+
+```toml
+[package]
+name = "Your embedded project"
+
+# Some parts omitted for brevity.
+
+[dependencies]
+tock-registers = "X.Y.Z"
+cortex-a = "A.B.C"       # <-- Includes tock-registers itself.
+```
+
+### Example
+
+Check out https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials for usage examples. Listed
+below is a snippet of `rust-raspberrypi-OS-tutorials`'s early boot code.
 
 ```rust
-unsafe fn el2_to_el1_transition() -> ! {
+use cortex_a::{asm, registers::*};
+use tock_registers::interfaces::Writeable; // <-- Trait needed to use `write()` and `set()`.
+
+// Some parts omitted for brevity.
+
+unsafe fn prepare_el2_to_el1_transition(
+    virt_boot_core_stack_end_exclusive_addr: u64,
+    virt_kernel_init_addr: u64,
+) {
     // Enable timer counter registers for EL1.
     CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
 

src/asm.rs

@@ -6,7 +6,9 @@
 //   - Jorge Aparicio
 //   - Andre Richter <[email protected]>
 
-//! Miscellaneous assembly instructions
+//! Wrappers around ARMv8-A instructions.
+
+pub mod barrier;
 
 /// The classic no-op
 #[inline(always)]
@@ -22,7 +24,7 @@ pub fn nop() {
 
 /// Wait For Interrupt
 ///
-/// For more details on wfi, refer to [here](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CIHEGBBF.html)
+/// For more details on wfi, refer to [here](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CIHEGBBF.html).
 #[inline(always)]
 pub fn wfi() {
     #[cfg(target_arch = "aarch64")]
@@ -36,7 +38,7 @@ pub fn wfi() {
 
 /// Wait For Event
 ///
-/// For more details of wfe - sev pair, refer to [here](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CIHEGBBF.html)
+/// For more details of wfe - sev pair, refer to [here](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CIHEGBBF.html).
 #[inline(always)]
 pub fn wfe() {
     #[cfg(target_arch = "aarch64")]
@@ -52,7 +54,7 @@ pub fn wfe() {
 ///
 /// SEV causes an event to be signaled to the local core within a multiprocessor system.
 ///
-/// For more details of wfe - sev/sevl pair, refer to [here](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CIHEGBBF.html)
+/// For more details of wfe - sev/sevl pair, refer to [here](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CIHEGBBF.html).
 #[inline(always)]
 pub fn sevl() {
     #[cfg(target_arch = "aarch64")]
@@ -68,7 +70,7 @@ pub fn sevl() {
 ///
 /// SEV causes an event to be signaled to all cores within a multiprocessor system.
 ///
-/// For more details of wfe - sev pair, refer to [here](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CIHEGBBF.html)
+/// For more details of wfe - sev pair, refer to [here](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CIHEGBBF.html).
 #[inline(always)]
 pub fn sev() {
     #[cfg(target_arch = "aarch64")]

src/barrier.rs renamed to src/asm/barrier.rs

@@ -5,10 +5,7 @@
 // Author(s):
 //   - Andre Richter <[email protected]>
 
-// Borrow implementations from the pending upstream ACLE implementation until it is merged.
-// Afterwards, we'll probably just reexport them, hoping that the API doesn't change.
-//
-// https://github.com/rust-lang-nursery/stdsimd/pull/557
+//! Barrier functions.
 
 mod sealed {
     pub trait Dmb {

src/lib.rs

@@ -7,17 +7,53 @@
 
 //! Low level access to Cortex-A processors.
 //!
-//! ## Currently Supported Architectures
+//! ## Currently Supported Execution States
 //!
 //! - [x] AArch64
 //! - [ ] AArch32
 //!
+//! ## Minimum Supported Rust Version
+//!
+//! Requires a recent nightly of Rust.
+//!
 //! ## Usage
 //!
-//! Example from https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials
+//! Please note that for using this crate's [register definitions](src/registers) (as provided by
+//! `cortex_a::registers::*`), you need to also include
+//! [`tock-registers`](https://crates.io/crates/tock-registers) in your project. This is because the
+//! `interface` traits provided by `tock-registers` are implemented by this crate. You should
+//! include the same version of `tock-registers` as is being used by this crate to ensure sane
+//! interoperatbility.
+//!
+//! For example, in the following snippet, `X.Y.Z` should be the same version of `tock-registers`
+//! that is mentioned in `cortex-a`'s [`Cargo.toml`](Cargo.toml).
+//!
+//! ```toml
+//! [package]
+//! name = "Your embedded project"
+//!
+//! # Some parts omitted for brevity.
+//!
+//! [dependencies]
+//! tock-registers = "X.Y.Z"
+//! cortex-a = "A.B.C"       # <-- Includes tock-registers itself.
+//! ```
+//!
+//! ### Example
+//!
+//! Check out https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials for usage examples.
+//! Listed below is a snippet of `rust-raspberrypi-OS-tutorials`'s early boot code.
 //!
 //! ```rust
-//! unsafe fn el2_to_el1_transition() -> ! {
+//! use cortex_a::{asm, registers::*};
+//! use tock_registers::interfaces::Writeable; // <-- Trait needed to use `write()` and `set()`.
+//!
+//! // Some parts omitted for brevity.
+//!
+//! unsafe fn prepare_el2_to_el1_transition(
+//!     virt_boot_core_stack_end_exclusive_addr: u64,
+//!     virt_kernel_init_addr: u64,
+//! ) {
 //!     // Enable timer counter registers for EL1.
 //!     CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
 //!
@@ -39,15 +75,14 @@
 //!
 //! ## Disclaimer
 //!
-//! Descriptive comments in the source files are taken from the
-//! [ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile](https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf?_ga=2.266626254.1122218691.1534883460-1326731866.1530967873).
+//! Descriptive comments in the source files are taken from the [ARM Architecture Reference Manual
+//! ARMv8, for ARMv8-A architecture
+//! profile](https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf?_ga=2.266626254.1122218691.1534883460-1326731866.1530967873).
 
-#![allow(clippy::clippy::upper_case_acronyms)]
+#![feature(asm)]
 #![feature(core_intrinsics)]
 #![feature(custom_inner_attributes)]
-#![feature(asm)]
 #![no_std]
 
 pub mod asm;
-pub mod barrier;
-pub mod regs;
+pub mod registers;

src/registers.rs

@@ -0,0 +1,99 @@
+//! Processor core registers
+
+#![allow(unused_attributes)]
+#![rustfmt::skip]
+
+#[macro_use]
+mod macros;
+
+mod cntfrq_el0;
+mod cnthctl_el2;
+mod cntp_ctl_el0;
+mod cntp_tval_el0;
+mod cntpct_el0;
+mod cntv_ctl_el0;
+mod cntv_tval_el0;
+mod cntvct_el0;
+mod cntvoff_el2;
+mod currentel;
+mod daif;
+mod elr_el1;
+mod elr_el2;
+mod elr_el3;
+mod esr_el1;
+mod esr_el2;
+mod far_el1;
+mod far_el2;
+mod hcr_el2;
+mod id_aa64mmfr0_el1;
+mod lr;
+mod mair_el1;
+mod mair_el2;
+mod midr_el1;
+mod mpidr_el1;
+mod par_el1;
+mod scr_el3;
+mod sctlr_el1;
+mod sctlr_el2;
+mod sp;
+mod sp_el0;
+mod sp_el1;
+mod spsel;
+mod spsr_el1;
+mod spsr_el2;
+mod spsr_el3;
+mod tcr_el1;
+mod tcr_el2;
+mod tpidr_el0;
+mod tpidr_el1;
+mod tpidrro_el0;
+mod ttbr0_el1;
+mod ttbr0_el2;
+mod ttbr1_el1;
+mod vbar_el1;
+
+pub use cntfrq_el0::CNTFRQ_EL0;
+pub use cnthctl_el2::CNTHCTL_EL2;
+pub use cntp_ctl_el0::CNTP_CTL_EL0;
+pub use cntp_tval_el0::CNTP_TVAL_EL0;
+pub use cntpct_el0::CNTPCT_EL0;
+pub use cntv_ctl_el0::CNTV_CTL_EL0;
+pub use cntv_tval_el0::CNTV_TVAL_EL0;
+pub use cntvct_el0::CNTVCT_EL0;
+pub use cntvoff_el2::CNTVOFF_EL2;
+pub use currentel::CurrentEL;
+pub use daif::DAIF;
+pub use elr_el1::ELR_EL1;
+pub use elr_el2::ELR_EL2;
+pub use elr_el3::ELR_EL3;
+pub use esr_el1::ESR_EL1;
+pub use esr_el2::ESR_EL2;
+pub use far_el1::FAR_EL1;
+pub use far_el2::FAR_EL2;
+pub use hcr_el2::HCR_EL2;
+pub use id_aa64mmfr0_el1::ID_AA64MMFR0_EL1;
+pub use lr::LR;
+pub use mair_el1::MAIR_EL1;
+pub use mair_el2::MAIR_EL2;
+pub use midr_el1::MIDR_EL1;
+pub use mpidr_el1::MPIDR_EL1;
+pub use par_el1::PAR_EL1;
+pub use scr_el3::SCR_EL3;
+pub use sctlr_el1::SCTLR_EL1;
+pub use sctlr_el2::SCTLR_EL2;
+pub use sp::SP;
+pub use sp_el0::SP_EL0;
+pub use sp_el1::SP_EL1;
+pub use spsel::SPSel;
+pub use spsr_el1::SPSR_EL1;
+pub use spsr_el2::SPSR_EL2;
+pub use spsr_el3::SPSR_EL3;
+pub use tcr_el1::TCR_EL1;
+pub use tcr_el2::TCR_EL2;
+pub use tpidr_el0::TPIDR_EL0;
+pub use tpidr_el1::TPIDR_EL1;
+pub use tpidrro_el0::TPIDRRO_EL0;
+pub use ttbr0_el1::TTBR0_EL1;
+pub use ttbr0_el2::TTBR0_EL2;
+pub use ttbr1_el1::TTBR1_EL1;
+pub use vbar_el1::VBAR_EL1;

src/regs/cntfrq_el0.rs renamed to src/registers/cntfrq_el0.rs

@@ -11,12 +11,15 @@
 //! must be programmed with this value as part of system initialization. The value of the register
 //! is not interpreted by hardware.
 
-use register::cpu::RegisterReadOnly;
+use tock_registers::interfaces::Readable;
 
 pub struct Reg;
 
-impl RegisterReadOnly<u64, ()> for Reg {
+impl Readable for Reg {
+    type T = u64;
+    type R = ();
+
     sys_coproc_read_raw!(u64, "CNTFRQ_EL0", "x");
 }
 
-pub static CNTFRQ_EL0: Reg = Reg {};
+pub const CNTFRQ_EL0: Reg = Reg {};