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5 | 5 | // Author(s):
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6 | 6 | // - Andre Richter <[email protected]>
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7 | 7 |
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8 |
| -//! Low level access to Cortex-A processors |
| 8 | +//! Low level access to Cortex-A processors. |
9 | 9 | //!
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10 |
| -//! This crate provides: |
| 10 | +//! ## Currently Supported Architectures |
11 | 11 | //!
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12 |
| -//! - Safe wrappers around assembly instructions |
| 12 | +//! - [x] AArch64 |
| 13 | +//! - [ ] AArch32 |
13 | 14 | //!
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14 |
| -//! For now, there's not much. I will update it gradually. |
15 |
| -//! If you want to contribute, feel free to reach out! |
| 15 | +//! ## Minimum Supported Rust Version |
16 | 16 | //!
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17 |
| -//! # Minimum Supported Rust Version (MSRV) |
| 17 | +//! Requires rustc 1.45.0 or later due to use of the new `asm!()` syntax. |
18 | 18 | //!
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19 |
| -//! This crate is guaranteed to compile on stable Rust 1.39 and up. It *might* compile with older |
20 |
| -//! versions but that may change in any new patch release. |
| 19 | +//! ## Usage |
| 20 | +//! |
| 21 | +//! Example from https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials |
| 22 | +//! |
| 23 | +//! ```rust |
| 24 | +//! unsafe fn el2_to_el1_transition() -> ! { |
| 25 | +//! // Enable timer counter registers for EL1. |
| 26 | +//! CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET); |
| 27 | +//! |
| 28 | +//! // No offset for reading the counters. |
| 29 | +//! CNTVOFF_EL2.set(0); |
| 30 | +//! |
| 31 | +//! // Set EL1 execution state to AArch64. |
| 32 | +//! HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64); |
| 33 | +//! |
| 34 | +//! // Set up a simulated exception return. |
| 35 | +//! SPSR_EL2.write( |
| 36 | +//! SPSR_EL2::D::Masked |
| 37 | +//! + SPSR_EL2::A::Masked |
| 38 | +//! + SPSR_EL2::I::Masked |
| 39 | +//! + SPSR_EL2::F::Masked |
| 40 | +//! + SPSR_EL2::M::EL1h, |
| 41 | +//! ); |
| 42 | +//! ``` |
| 43 | +//! |
| 44 | +//! ## Disclaimer |
| 45 | +//! |
| 46 | +//! Descriptive comments in the source files are taken from the |
| 47 | +//! [ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile](https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf?_ga=2.266626254.1122218691.1534883460-1326731866.1530967873). |
21 | 48 |
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22 | 49 | #![feature(core_intrinsics)]
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23 | 50 | #![feature(custom_inner_attributes)]
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