add a lot of register derives + serde support for cortex-ar

Author: robamu

.github/workflows/build.yml

@@ -38,7 +38,7 @@ jobs:
           rustup target add ${{ matrix.target }}
       - name: Build
         run: |
-          cargo build --target ${{ matrix.target }}
+          cargo build --target ${{ matrix.target }} --features "serde, defmt"
           cargo build --target ${{ matrix.target }} --no-default-features
 
   build-versatileab:

cortex-ar/CHANGELOG.md

@@ -17,6 +17,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   maintenance by MVA (specific address).
 - Added new  `L1Section::set_section_attrs` and `L1Section::section_attrs` method. Also added
   low-level `L1Section::new_with_addr_upper_bits_and_attrs` constructor.
+- optional `serde` derives behind a `serde` feature gate
+- lots of missing `Debug`, `Copy`, `Clone`, `defmt::Format` derives.
 
 ### Changed
 

cortex-ar/Cargo.toml

@@ -26,11 +26,12 @@ version = "0.2.0"
 
 [dependencies]
 arbitrary-int = "2"
-bitbybit = "1.3.3"
+bitbybit = "1.4"
 num_enum = { version = "0.7", default-features = false }
 critical-section = {version = "1.2.0", features = ["restore-state-u8"], optional = true}
 thiserror = { version = "2", default-features = false }
-defmt = {version = "1", optional = true}
+defmt = { version = "1", optional = true }
+serde = { version = "1", features = ["derive"], default-features = false, optional = true }
 
 [build-dependencies]
 arm-targets = {version = "0.2.0", path = "../arm-targets"}
@@ -44,6 +45,7 @@ critical-section-single-core = ["critical-section"]
 critical-section-multi-core = ["critical-section"]
 # Adds defmt::Format implementation for the register types
 defmt = ["dep:defmt", "arbitrary-int/defmt"]
+serde = ["dep:serde", "arbitrary-int/serde"]
 
 [package.metadata.docs.rs]
 targets = ["armv7r-none-eabihf", "armv7r-none-eabi", "armv7a-none-eabihf"]

cortex-ar/src/mmu.rs

@@ -2,11 +2,13 @@ use arbitrary_int::{u12, u2, u3, u4};
 
 #[derive(Debug, thiserror::Error)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[error("invalid L1 entry type {0:?}")]
 pub struct InvalidL1EntryType(pub L1EntryType);
 
 #[bitbybit::bitenum(u3, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
 pub enum AccessPermissions {
     PermissionFault = 0b000,
@@ -40,6 +42,7 @@ impl AccessPermissions {
 
 #[bitbybit::bitenum(u2, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum L1EntryType {
@@ -60,6 +63,7 @@ pub enum L1EntryType {
 /// of the B, C, and TEX bits.
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct MemoryRegionAttributesRaw {
     /// TEX bits
     type_extensions: u3,
@@ -80,6 +84,7 @@ impl MemoryRegionAttributesRaw {
 
 #[bitbybit::bitenum(u2, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug)]
 pub enum CacheableMemoryAttribute {
     NonCacheable = 0b00,
@@ -90,6 +95,7 @@ pub enum CacheableMemoryAttribute {
 
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub enum MemoryRegionAttributes {
     StronglyOrdered,
     ShareableDevice,
@@ -142,6 +148,7 @@ impl MemoryRegionAttributes {
 /// Individual section attributes for a L1 section.
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct SectionAttributes {
     /// NG bit
     pub non_global: bool,
@@ -205,7 +212,8 @@ impl SectionAttributes {
 ///
 /// The ARM Cortex-A architecture programmers manual chapter 9.4 (p.163) or the ARMv7-A and ArmV7-R
 /// architecture reference manual p.1323 specify these attributes in more detail.
-#[bitbybit::bitfield(u32, default = 0x00)]
+#[bitbybit::bitfield(u32, default = 0, defmt_fields(feature = "defmt"))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(PartialEq, Eq)]
 pub struct L1Section {
     /// Section base address upper bits.

cortex-ar/src/pmsav7.rs

@@ -13,6 +13,7 @@ pub use register::drsr::RegionSize;
 
 /// Ways this API can fail
 #[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
     /// Found too many regions
     TooManyRegions,

cortex-ar/src/register/actlr.rs

@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// ACTLR (*Auxiliary Control Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Actlr(pub u32);
 impl SysReg for Actlr {
     const CP: u32 = 15;

cortex-ar/src/register/actlr2.rs

@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// ACTLR2 (*Auxiliary Control Register 2*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Actlr2(pub u32);
 impl SysReg for Actlr2 {
     const CP: u32 = 15;

cortex-ar/src/register/adfsr.rs

@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// ADFSR (*Auxiliary Data Fault Status Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Adfsr(pub u32);
 impl SysReg for Adfsr {
     const CP: u32 = 15;

cortex-ar/src/register/aidr.rs

@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead};
 
 /// AIDR (*Auxiliary ID Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Aidr(pub u32);
 impl SysReg for Aidr {
     const CP: u32 = 15;

cortex-ar/src/register/aifsr.rs

@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// AIFSR (*Auxiliary Instruction Fault Status Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Aifsr(pub u32);
 impl SysReg for Aifsr {
     const CP: u32 = 15;