Merge #160

160: Update for 2018 edition r=korken89 a=adamgreig



Co-authored-by: Adam Greig <[email protected]>

Author: bors[bot]

CHANGELOG.md

@@ -302,10 +302,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 #![feature(used)]
 #![no_std]
 
-extern crate cortex_m;
-extern crate cortex_m_rt;
-extern crate stm32f30x;
-
 use core::cell::RefCell;
 
 use cortex_m::ctxt::Local;

Cargo.toml

@@ -12,6 +12,7 @@ name = "cortex-m"
 readme = "README.md"
 repository = "https://github.com/japaric/cortex-m"
 version = "0.6.0"
+edition = "2018"
 links = "cortex-m"  # prevent multiple versions of this crate to be linked together
 
 [dependencies]

src/interrupt.rs

@@ -61,7 +61,7 @@ pub fn free<F, R>(f: F) -> R
 where
     F: FnOnce(&CriticalSection) -> R,
 {
-    let primask = ::register::primask::read();
+    let primask = crate::register::primask::read();
 
     // disable interrupts
     disable();

src/itm.rs

@@ -6,7 +6,7 @@ use core::{fmt, mem, ptr, slice};
 
 use aligned::{Aligned, A4};
 
-use peripheral::itm::Stim;
+use crate::peripheral::itm::Stim;
 
 // NOTE assumes that `bytes` is 32-bit aligned
 unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) {

src/lib.rs

@@ -47,4 +47,4 @@ pub mod itm;
 pub mod peripheral;
 pub mod register;
 
-pub use peripheral::Peripherals;
+pub use crate::peripheral::Peripherals;

src/macros.rs

@@ -33,8 +33,7 @@ macro_rules! iprintln {
 /// # Example
 ///
 /// ``` no_run
-/// #[macro_use(singleton)]
-/// extern crate cortex_m;
+/// use cortex_m::singleton;
 ///
 /// fn main() {
 ///     // OK if `main` is executed only once
@@ -77,8 +76,7 @@ macro_rules! singleton {
 }
 
 /// ``` compile_fail
-/// #[macro_use(singleton)]
-/// extern crate cortex_m;
+/// use cortex_m::singleton;
 ///
 /// fn main() {}
 ///
@@ -92,8 +90,7 @@ const CFAIL: () = ();
 
 /// ```
 /// #![deny(unsafe_code)]
-/// #[macro_use(singleton)]
-/// extern crate cortex_m;
+/// use cortex_m::singleton;
 ///
 /// fn main() {}
 ///

src/peripheral/cbp.rs

@@ -4,7 +4,7 @@
 
 use volatile_register::WO;
 
-use peripheral::CBP;
+use crate::peripheral::CBP;
 
 /// Register block
 #[repr(C)]

src/peripheral/cpuid.rs

@@ -5,7 +5,7 @@ use volatile_register::RO;
 use volatile_register::RW;
 
 #[cfg(not(armv6m))]
-use peripheral::CPUID;
+use crate::peripheral::CPUID;
 
 /// Register block
 #[repr(C)]
@@ -104,7 +104,7 @@ impl CPUID {
         const CCSIDR_ASSOCIATIVITY_MASK: u32 = 0x3FF << CCSIDR_ASSOCIATIVITY_POS;
 
         self.select_cache(level, ind);
-        ::asm::dsb();
+        crate::asm::dsb();
         let ccsidr = self.ccsidr.read();
         (
             (1 + ((ccsidr & CCSIDR_NUMSETS_MASK) >> CCSIDR_NUMSETS_POS)) as u16,

src/peripheral/dcb.rs

@@ -3,7 +3,7 @@
 use volatile_register::{RW, WO};
 
 use core::ptr;
-use peripheral::DCB;
+use crate::peripheral::DCB;
 
 const DCB_DEMCR_TRCENA: u32 = 1 << 24;
 

src/peripheral/dwt.rs

@@ -4,7 +4,7 @@
 use volatile_register::WO;
 use volatile_register::{RO, RW};
 
-use peripheral::DWT;
+use crate::peripheral::DWT;
 
 /// Register block
 #[repr(C)]