Skip to content

Commit 7d51707

Browse files
japaricjaparic
committed
simplify #[cfg]s
1 parent 2cd6092 commit 7d51707

File tree

5 files changed

+57
-55
lines changed

5 files changed

+57
-55
lines changed

‎CHANGELOG.md

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
2323
- [breaking-change] Some variants of the `Exception` enumeration are no longer available on
2424
`thumbv6m-none-eabi`. See API docs for details.
2525

26+
- [breaking-change] Several of the variants of the `Exception` enumeration have been renamed to
27+
match the CMSIS specification.
28+
2629
- [breaking-change] fixed typo in `shcrs` field of `scb::RegisterBlock`; it was previously named
2730
`shpcrs`.
2831

‎src/lib.rs

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,8 +45,7 @@ mod macros;
4545

4646
pub mod asm;
4747
pub mod interrupt;
48-
// NOTE(target_arch = "x86_64") is used throughout this crate for documentation purposes
49-
#[cfg(any(armv7m, target_arch = "x86_64"))]
48+
#[cfg(not(armv6m))]
5049
pub mod itm;
5150
pub mod peripheral;
5251
pub mod register;

‎src/peripheral/cpuid.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ pub struct RegisterBlock {
6565
}
6666

6767
/// Type of cache to select on CSSELR writes.
68-
#[cfg(any(armv7m, target_arch = "x86_64"))]
68+
#[cfg(not(armv6m))]
6969
pub enum CsselrCacheType {
7070
/// Select DCache or unified cache
7171
DataOrUnified = 0,

‎src/peripheral/mod.rs

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -84,23 +84,23 @@ use core::ops;
8484

8585
use interrupt;
8686

87-
// NOTE(target_arch) is for documentation purposes
88-
#[cfg(any(armv7m, target_arch = "x86_64"))]
87+
#[cfg(not(armv6m))]
8988
pub mod cbp;
9089
pub mod cpuid;
9190
pub mod dcb;
9291
pub mod dwt;
93-
#[cfg(any(armv7m, target_arch = "x86_64"))]
92+
#[cfg(not(armv6m))]
9493
pub mod fpb;
94+
// NOTE(target_arch) is for documentation purposes
9595
#[cfg(any(has_fpu, target_arch = "x86_64"))]
9696
pub mod fpu;
97-
#[cfg(any(armv7m, target_arch = "x86_64"))]
97+
#[cfg(not(armv6m))]
9898
pub mod itm;
9999
pub mod mpu;
100100
pub mod nvic;
101101
pub mod scb;
102102
pub mod syst;
103-
#[cfg(any(armv7m, target_arch = "x86_64"))]
103+
#[cfg(not(armv6m))]
104104
pub mod tpiu;
105105

106106
#[cfg(test)]
@@ -112,7 +112,7 @@ mod test;
112112
#[allow(non_snake_case)]
113113
pub struct Peripherals {
114114
/// Cache and branch predictor maintenance operations
115-
#[cfg(any(armv7m, target_arch = "x86_64"))]
115+
#[cfg(not(armv6m))]
116116
pub CBP: CBP,
117117
/// CPUID
118118
pub CPUID: CPUID,
@@ -121,13 +121,13 @@ pub struct Peripherals {
121121
/// Data Watchpoint and Trace unit
122122
pub DWT: DWT,
123123
/// Flash Patch and Breakpoint unit
124-
#[cfg(any(armv7m, target_arch = "x86_64"))]
124+
#[cfg(not(armv6m))]
125125
pub FPB: FPB,
126126
/// Floating Point Unit
127127
#[cfg(any(has_fpu, target_arch = "x86_64"))]
128128
pub FPU: FPU,
129129
/// Instrumentation Trace Macrocell
130-
#[cfg(any(armv7m, target_arch = "x86_64"))]
130+
#[cfg(not(armv6m))]
131131
pub ITM: ITM,
132132
/// Memory Protection Unit
133133
pub MPU: MPU,
@@ -138,7 +138,7 @@ pub struct Peripherals {
138138
/// SysTick: System Timer
139139
pub SYST: SYST,
140140
/// Trace Port Interface Unit;
141-
#[cfg(any(armv7m, target_arch = "x86_64"))]
141+
#[cfg(not(armv6m))]
142142
pub TPIU: TPIU,
143143
}
144144

@@ -167,7 +167,7 @@ impl Peripherals {
167167
CORE_PERIPHERALS = true;
168168

169169
Peripherals {
170-
#[cfg(any(armv7m, target_arch = "x86_64"))]
170+
#[cfg(not(armv6m))]
171171
CBP: CBP {
172172
_marker: PhantomData,
173173
},
@@ -180,15 +180,15 @@ impl Peripherals {
180180
DWT: DWT {
181181
_marker: PhantomData,
182182
},
183-
#[cfg(any(armv7m, target_arch = "x86_64"))]
183+
#[cfg(not(armv6m))]
184184
FPB: FPB {
185185
_marker: PhantomData,
186186
},
187187
#[cfg(any(has_fpu, target_arch = "x86_64"))]
188188
FPU: FPU {
189189
_marker: PhantomData,
190190
},
191-
#[cfg(any(armv7m, target_arch = "x86_64"))]
191+
#[cfg(not(armv6m))]
192192
ITM: ITM {
193193
_marker: PhantomData,
194194
},
@@ -204,7 +204,7 @@ impl Peripherals {
204204
SYST: SYST {
205205
_marker: PhantomData,
206206
},
207-
#[cfg(any(armv7m, target_arch = "x86_64"))]
207+
#[cfg(not(armv6m))]
208208
TPIU: TPIU {
209209
_marker: PhantomData,
210210
},
@@ -215,15 +215,15 @@ impl Peripherals {
215215
/// Cache and branch predictor maintenance operations
216216
///
217217
/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
218-
#[cfg(any(armv7m, target_arch = "x86_64"))]
218+
#[cfg(not(armv6m))]
219219
pub struct CBP {
220220
_marker: PhantomData<*const ()>,
221221
}
222222

223-
#[cfg(any(armv7m, target_arch = "x86_64"))]
223+
#[cfg(not(armv6m))]
224224
unsafe impl Send for CBP {}
225225

226-
#[cfg(any(armv7m, target_arch = "x86_64"))]
226+
#[cfg(not(armv6m))]
227227
impl CBP {
228228
pub(crate) unsafe fn new() -> Self {
229229
CBP {
@@ -237,7 +237,7 @@ impl CBP {
237237
}
238238
}
239239

240-
#[cfg(any(armv7m, target_arch = "x86_64"))]
240+
#[cfg(not(armv6m))]
241241
impl ops::Deref for CBP {
242242
type Target = self::cbp::RegisterBlock;
243243

@@ -315,23 +315,23 @@ impl ops::Deref for DWT {
315315
/// Flash Patch and Breakpoint unit
316316
///
317317
/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
318-
#[cfg(any(armv7m, target_arch = "x86_64"))]
318+
#[cfg(not(armv6m))]
319319
pub struct FPB {
320320
_marker: PhantomData<*const ()>,
321321
}
322322

323-
#[cfg(any(armv7m, target_arch = "x86_64"))]
323+
#[cfg(not(armv6m))]
324324
unsafe impl Send for FPB {}
325325

326-
#[cfg(any(armv7m, target_arch = "x86_64"))]
326+
#[cfg(not(armv6m))]
327327
impl FPB {
328328
/// Returns a pointer to the register block
329329
pub fn ptr() -> *const fpb::RegisterBlock {
330330
0xE000_2000 as *const _
331331
}
332332
}
333333

334-
#[cfg(any(armv7m, target_arch = "x86_64"))]
334+
#[cfg(not(armv6m))]
335335
impl ops::Deref for FPB {
336336
type Target = self::fpb::RegisterBlock;
337337

@@ -371,23 +371,23 @@ impl ops::Deref for FPU {
371371
/// Instrumentation Trace Macrocell
372372
///
373373
/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
374-
#[cfg(any(armv7m, target_arch = "x86_64"))]
374+
#[cfg(not(armv6m))]
375375
pub struct ITM {
376376
_marker: PhantomData<*const ()>,
377377
}
378378

379-
#[cfg(any(armv7m, target_arch = "x86_64"))]
379+
#[cfg(not(armv6m))]
380380
unsafe impl Send for ITM {}
381381

382-
#[cfg(any(armv7m, target_arch = "x86_64"))]
382+
#[cfg(not(armv6m))]
383383
impl ITM {
384384
/// Returns a pointer to the register block
385385
pub fn ptr() -> *mut itm::RegisterBlock {
386386
0xE000_0000 as *mut _
387387
}
388388
}
389389

390-
#[cfg(any(armv7m, target_arch = "x86_64"))]
390+
#[cfg(not(armv6m))]
391391
impl ops::Deref for ITM {
392392
type Target = self::itm::RegisterBlock;
393393

@@ -396,7 +396,7 @@ impl ops::Deref for ITM {
396396
}
397397
}
398398

399-
#[cfg(any(armv7m, target_arch = "x86_64"))]
399+
#[cfg(not(armv6m))]
400400
impl ops::DerefMut for ITM {
401401
fn deref_mut(&mut self) -> &mut Self::Target {
402402
unsafe { &mut *Self::ptr() }
@@ -494,23 +494,23 @@ impl ops::Deref for SYST {
494494
/// Trace Port Interface Unit;
495495
///
496496
/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
497-
#[cfg(any(armv7m, target_arch = "x86_64"))]
497+
#[cfg(not(armv6m))]
498498
pub struct TPIU {
499499
_marker: PhantomData<*const ()>,
500500
}
501501

502-
#[cfg(any(armv7m, target_arch = "x86_64"))]
502+
#[cfg(not(armv6m))]
503503
unsafe impl Send for TPIU {}
504504

505-
#[cfg(any(armv7m, target_arch = "x86_64"))]
505+
#[cfg(not(armv6m))]
506506
impl TPIU {
507507
/// Returns a pointer to the register block
508508
pub fn ptr() -> *const tpiu::RegisterBlock {
509509
0xE004_0000 as *const _
510510
}
511511
}
512512

513-
#[cfg(any(armv7m, target_arch = "x86_64"))]
513+
#[cfg(not(armv6m))]
514514
impl ops::Deref for TPIU {
515515
type Target = self::tpiu::RegisterBlock;
516516

‎src/peripheral/scb.rs

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -4,11 +4,11 @@ use core::ptr;
44

55
use volatile_register::RW;
66

7-
#[cfg(any(armv7m, target_arch = "x86_64"))]
7+
#[cfg(not(armv6m))]
88
use super::cpuid::CsselrCacheType;
9-
#[cfg(any(armv7m, target_arch = "x86_64"))]
9+
#[cfg(not(armv6m))]
1010
use super::CPUID;
11-
#[cfg(any(armv7m, has_fpu, target_arch = "x86_64"))]
11+
#[cfg(not(armv6m))]
1212
use super::CBP;
1313
use super::SCB;
1414

@@ -172,16 +172,16 @@ impl SCB {
172172
0 => VectActive::ThreadMode,
173173
2 => VectActive::Exception(Exception::NonMaskableInt),
174174
3 => VectActive::Exception(Exception::HardFault),
175-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
175+
#[cfg(not(armv6m))]
176176
4 => VectActive::Exception(Exception::MemoryManagement),
177-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
177+
#[cfg(not(armv6m))]
178178
5 => VectActive::Exception(Exception::BusFault),
179-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
179+
#[cfg(not(armv6m))]
180180
6 => VectActive::Exception(Exception::UsageFault),
181181
#[cfg(any(armv8m, target_arch = "x86_64"))]
182182
7 => VectActive::Exception(Exception::SecureFault),
183183
11 => VectActive::Exception(Exception::SVCall),
184-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
184+
#[cfg(not(armv6m))]
185185
12 => VectActive::Exception(Exception::DebugMonitor),
186186
14 => VectActive::Exception(Exception::PendSV),
187187
15 => VectActive::Exception(Exception::SysTick),
@@ -200,15 +200,15 @@ pub enum Exception {
200200
HardFault,
201201

202202
/// Memory management interrupt (not present on Cortex-M0 variants)
203-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
203+
#[cfg(not(armv6m))]
204204
MemoryManagement,
205205

206206
/// Bus fault interrupt (not present on Cortex-M0 variants)
207-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
207+
#[cfg(not(armv6m))]
208208
BusFault,
209209

210210
/// Usage fault interrupt (not present on Cortex-M0 variants)
211-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
211+
#[cfg(not(armv6m))]
212212
UsageFault,
213213

214214
/// Secure fault interrupt (only on ARMv8-M)
@@ -219,7 +219,7 @@ pub enum Exception {
219219
SVCall,
220220

221221
/// Debug monitor interrupt (not present on Cortex-M0 variants)
222-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
222+
#[cfg(not(armv6m))]
223223
DebugMonitor,
224224

225225
/// Pend SV interrupt
@@ -237,16 +237,16 @@ impl Exception {
237237
match *self {
238238
Exception::NonMaskableInt => -14,
239239
Exception::HardFault => -13,
240-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
240+
#[cfg(not(armv6m))]
241241
Exception::MemoryManagement => -12,
242-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
242+
#[cfg(not(armv6m))]
243243
Exception::BusFault => -11,
244-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
244+
#[cfg(not(armv6m))]
245245
Exception::UsageFault => -10,
246246
#[cfg(any(armv8m, target_arch = "x86_64"))]
247247
Exception::SecureFault => -9,
248248
Exception::SVCall => -5,
249-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
249+
#[cfg(not(armv6m))]
250250
Exception::DebugMonitor => -4,
251251
Exception::PendSV => -2,
252252
Exception::SysTick => -1,
@@ -277,16 +277,16 @@ impl VectActive {
277277
0 => VectActive::ThreadMode,
278278
2 => VectActive::Exception(Exception::NonMaskableInt),
279279
3 => VectActive::Exception(Exception::HardFault),
280-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
280+
#[cfg(not(armv6m))]
281281
4 => VectActive::Exception(Exception::MemoryManagement),
282-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
282+
#[cfg(not(armv6m))]
283283
5 => VectActive::Exception(Exception::BusFault),
284-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
284+
#[cfg(not(armv6m))]
285285
6 => VectActive::Exception(Exception::UsageFault),
286286
#[cfg(any(armv8m, target_arch = "x86_64"))]
287287
7 => VectActive::Exception(Exception::SecureFault),
288288
11 => VectActive::Exception(Exception::SVCall),
289-
#[cfg(any(not(armv6m), target_arch = "x86_64"))]
289+
#[cfg(not(armv6m))]
290290
12 => VectActive::Exception(Exception::DebugMonitor),
291291
14 => VectActive::Exception(Exception::PendSV),
292292
15 => VectActive::Exception(Exception::SysTick),
@@ -296,16 +296,16 @@ impl VectActive {
296296
}
297297
}
298298

299-
#[cfg(any(armv7m, target_arch = "x86_64"))]
299+
#[cfg(not(armv6m))]
300300
mod scb_consts {
301301
pub const SCB_CCR_IC_MASK: u32 = (1 << 17);
302302
pub const SCB_CCR_DC_MASK: u32 = (1 << 16);
303303
}
304304

305-
#[cfg(any(armv7m, target_arch = "x86_64"))]
305+
#[cfg(not(armv6m))]
306306
use self::scb_consts::*;
307307

308-
#[cfg(any(armv7m, target_arch = "x86_64"))]
308+
#[cfg(not(armv6m))]
309309
impl SCB {
310310
/// Enables I-Cache if currently disabled
311311
#[inline]

0 commit comments

Comments
 (0)