ARMv6-M: remove fields that are not available from NVIC and SCB

Author: japaric

CHANGELOG.md

@@ -23,6 +23,21 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - [breaking-change] Some variants of the `Exception` enumeration are no longer available on
   `thumbv6m-none-eabi`. See API docs for details.
 
+- [breaking-change] fixed typo in `shcrs` field of `scb::RegisterBlock`; it was previously named
+  `shpcrs`.
+
+- [breaking-change] removed several fields from `scb::RegisterBlock` on ARMv6-M. These registers are
+  not available on that sub-architecture.
+
+- [breaking-change] changed the type of `scb::RegisterBlock.shpr` from `RW<u8>` to `RW<u32>` on
+  ARMv6-M. These registers are word accessible only on that sub-architecture.
+
+- [breaking-change] renamed the `mmar` field of `scb::RegisterBlock` to `mmfar` to match the CMSIS
+  name.
+
+- [breaking-change] removed the `iabr` field from `scb::RegisterBlock` on ARMv6-M. This register is
+  not available on that sub-architecture.
+
 ### Removed
 
 - [breaking-change] The `exception` module has been removed. A replacement for `Exception::active`

src/peripheral/nvic.rs

@@ -1,6 +1,8 @@
 //! Nested Vector Interrupt Controller
 
-use volatile_register::{RO, RW};
+#[cfg(not(armv6m))]
+use volatile_register::RO;
+use volatile_register::RW;
 
 use interrupt::Nr;
 use peripheral::NVIC;
@@ -10,19 +12,31 @@ use peripheral::NVIC;
 pub struct RegisterBlock {
     /// Interrupt Set-Enable
     pub iser: [RW<u32>; 16],
-    reserved0: [u32; 16],
+
+    _reserved0: [u32; 16],
+
     /// Interrupt Clear-Enable
     pub icer: [RW<u32>; 16],
-    reserved1: [u32; 16],
+
+    _reserved1: [u32; 16],
+
     /// Interrupt Set-Pending
     pub ispr: [RW<u32>; 16],
-    reserved2: [u32; 16],
+
+    _reserved2: [u32; 16],
+
     /// Interrupt Clear-Pending
     pub icpr: [RW<u32>; 16],
-    reserved3: [u32; 16],
-    /// Interrupt Active Bit
+
+    _reserved3: [u32; 16],
+
+    /// Interrupt Active Bit (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
     pub iabr: [RO<u32>; 16],
-    reserved4: [u32; 48],
+    #[cfg(armv6m)]
+    _reserved4: [u32; 16],
+
+    _reserved5: [u32; 48],
 
     #[cfg(not(armv6m))]
     /// Interrupt Priority
@@ -110,6 +124,7 @@ impl NVIC {
     }
 
     /// Is `interrupt` active or pre-empted and stacked
+    #[cfg(not(armv6m))]
     pub fn is_active<I>(interrupt: I) -> bool
     where
         I: Nr,

src/peripheral/scb.rs

@@ -17,33 +17,85 @@ use super::SCB;
 pub struct RegisterBlock {
     /// Interrupt Control and State
     pub icsr: RW<u32>,
-    /// Vector Table Offset
+
+    /// Vector Table Offset (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
     pub vtor: RW<u32>,
+    #[cfg(armv6m)]
+    _reserved0: u32,
+
     /// Application Interrupt and Reset Control
     pub aircr: RW<u32>,
+
     /// System Control
     pub scr: RW<u32>,
+
     /// Configuration and Control
     pub ccr: RW<u32>,
-    /// System Handler Priority
+
+    /// System Handler Priority (word accessible only on Cortex-M0 variants)
+    ///
+    /// On ARMv7-M, `shpr[0]` points to SHPR1
+    ///
+    /// On ARMv6-M, `shpr[0]` points to SHPR2
+    #[cfg(not(armv6m))]
     pub shpr: [RW<u8>; 12],
+    #[cfg(armv6m)]
+    _reserved1: u32,
+    /// System Handler Priority (word accessible only on Cortex-M0 variants)
+    ///
+    /// On ARMv7-M, `shpr[0]` points to SHPR1
+    ///
+    /// On ARMv6-M, `shpr[0]` points to SHPR2
+    #[cfg(armv6m)]
+    pub shpr: [RW<u32>; 2],
+
     /// System Handler Control and State
-    pub shpcrs: RW<u32>,
-    /// Configurable Fault Status
+    pub shcrs: RW<u32>,
+
+    /// Configurable Fault Status (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
     pub cfsr: RW<u32>,
-    /// HardFault Status
+    #[cfg(armv6m)]
+    _reserved2: u32,
+
+    /// HardFault Status (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
     pub hfsr: RW<u32>,
-    /// Debug Fault Status
+    #[cfg(armv6m)]
+    _reserved3: u32,
+
+    /// Debug Fault Status (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
     pub dfsr: RW<u32>,
-    /// MemManage Fault Address
-    pub mmar: RW<u32>,
-    /// BusFault Address
+    #[cfg(armv6m)]
+    _reserved4: u32,
+
+    /// MemManage Fault Address (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub mmfar: RW<u32>,
+    #[cfg(armv6m)]
+    _reserved5: u32,
+
+    /// BusFault Address (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
     pub bfar: RW<u32>,
-    /// Auxiliary Fault Status
+    #[cfg(armv6m)]
+    _reserved6: u32,
+
+    /// Auxiliary Fault Status (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
     pub afsr: RW<u32>,
-    reserved: [u32; 18],
-    /// Coprocessor Access Control
+    #[cfg(armv6m)]
+    _reserved7: u32,
+
+    _reserved8: [u32; 18],
+
+    /// Coprocessor Access Control (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
     pub cpacr: RW<u32>,
+    #[cfg(armv6m)]
+    _reserved9: u32,
 }
 
 /// FPU access mode