cortex-m-rt: Add optional MSPLIM initialization for ARMv8-M Mainline

Author: decaday

cortex-m-rt/CHANGELOG.md

@@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Add `set_msplim` feature to conditionally set the MSPLIM register at device
+  reset ([#580]).
+
 ## [v0.7.5]
 
 - Fix incorrect dependency on cortex-m-rt-macros in v0.7.4 which led to

cortex-m-rt/Cargo.toml

@@ -45,6 +45,7 @@ required-features = ["device"]
 device = []
 set-sp = []
 set-vtor = []
+set-msplim = []
 zero-init-ram = []
 paint-stack = []
 

cortex-m-rt/build.rs

@@ -43,22 +43,36 @@ INCLUDE device.x"#
     };
 
     println!("cargo:rustc-check-cfg=cfg(armv6m)");
+    println!("cargo:rustc-check-cfg=cfg(armv7em)");
     println!("cargo:rustc-check-cfg=cfg(armv7m)");
     println!("cargo:rustc-check-cfg=cfg(armv8m)");
+    println!("cargo:rustc-check-cfg=cfg(armv8m_base)");
+    println!("cargo:rustc-check-cfg=cfg(armv8m_main)");
     println!("cargo:rustc-check-cfg=cfg(cortex_m)");
     println!("cargo:rustc-check-cfg=cfg(has_fpu)");
 
     let max_int_handlers = if target.starts_with("thumbv6m-") {
         println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv6m");
         32
-    } else if target.starts_with("thumbv7m-") || target.starts_with("thumbv7em-") {
+    } else if target.starts_with("thumbv7m-") {
         println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv7m");
         240
-    } else if target.starts_with("thumbv8m") {
+    } else if target.starts_with("thumbv7em-") {
+        println!("cargo:rustc-cfg=cortex_m");
+        println!("cargo:rustc-cfg=armv7m");
+        println!("cargo:rustc-cfg=armv7em");
+        240
+    } else if target.starts_with("thumbv8m.base") {
+        println!("cargo:rustc-cfg=cortex_m");
+        println!("cargo:rustc-cfg=armv8m");
+        println!("cargo:rustc-cfg=armv8m_base");
+        496
+    } else if target.starts_with("thumbv8m.main") {
         println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv8m");
+        println!("cargo:rustc-cfg=armv8m_main");
         496
     } else {
         // Non ARM target. We assume you're just testing the syntax.

cortex-m-rt/src/lib.rs

@@ -187,6 +187,13 @@
 //! required, but some bootloaders do not set VTOR before jumping to application code, leading to
 //! your main function executing but interrupt handlers not being used.
 //!
+//! ## `set-msplim`
+//!
+//! If this feature is enabled, the main stack pointer limit register (MSPLIM) is initialized in 
+//! the reset handler to the `_stack_end` value from the linker script. This feature is only 
+//! available on ARMv8-M Mainline and helps enforce stack limits by defining the lowest valid 
+//! stack address.
+//!
 //! ## `zero-init-ram`
 //!
 //! If this feature is enabled, RAM is initialized with zeros during startup from the `_ram_start`
@@ -544,6 +551,13 @@ cfg_global_asm! {
      ldr r1, =__vector_table
      str r1, [r0]",
 
+    // If enabled, set the Main Stack Pointer Limit (MSPLIM) to the end of the stack. 
+    // This feature is only available on ARMv8-M Mainline, where it helps enforce stack limits 
+    // by defining the lowest valid stack address.
+    #[cfg(all(armv8m_main, feature = "set-msplim"))]
+    "ldr r0, =_stack_end
+     msr MSPLIM, r0",
+
     // Run user pre-init code which must be executed immediately after startup, before the
     // potentially time-consuming memory initialisation takes place.
     // Example use cases include disabling default watchdogs or enabling RAM.