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//! SPI bus sharing mechanisms.
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- use embedded_hal:: delay:: DelayUs ;
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+ use embedded_hal:: delay:: DelayNs ;
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use embedded_hal:: digital:: OutputPin ;
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use embedded_hal:: spi:: { ErrorType , Operation , SpiBus , SpiDevice } ;
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#[ cfg( feature = "async" ) ]
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use embedded_hal_async:: {
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- delay:: DelayUs as AsyncDelayUs ,
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+ delay:: DelayNs as AsyncDelayNs ,
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spi:: { SpiBus as AsyncSpiBus , SpiDevice as AsyncSpiDevice } ,
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} ;
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+ use super :: shared:: transaction;
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use super :: DeviceError ;
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/// [`SpiDevice`] implementation with exclusive access to the bus (not shared).
@@ -47,7 +48,7 @@ impl<BUS, CS> ExclusiveDevice<BUS, CS, super::NoDelay> {
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/// # Panics
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///
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/// The returned device will panic if you try to execute a transaction
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- /// that contains any operations of type `Operation::DelayUs` .
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+ /// that contains any operations of type [ `Operation::DelayNs`] .
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#[ inline]
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pub fn new_no_delay ( bus : BUS , cs : CS ) -> Self {
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Self {
@@ -70,33 +71,11 @@ impl<Word: Copy + 'static, BUS, CS, D> SpiDevice<Word> for ExclusiveDevice<BUS,
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where
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BUS : SpiBus < Word > ,
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CS : OutputPin ,
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- D : DelayUs ,
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+ D : DelayNs ,
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{
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#[ inline]
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fn transaction ( & mut self , operations : & mut [ Operation < ' _ , Word > ] ) -> Result < ( ) , Self :: Error > {
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- self . cs . set_low ( ) . map_err ( DeviceError :: Cs ) ?;
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-
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- let op_res = operations. iter_mut ( ) . try_for_each ( |op| match op {
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- Operation :: Read ( buf) => self . bus . read ( buf) ,
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- Operation :: Write ( buf) => self . bus . write ( buf) ,
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- Operation :: Transfer ( read, write) => self . bus . transfer ( read, write) ,
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- Operation :: TransferInPlace ( buf) => self . bus . transfer_in_place ( buf) ,
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- Operation :: DelayUs ( us) => {
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- self . bus . flush ( ) ?;
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- self . delay . delay_us ( * us) ;
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- Ok ( ( ) )
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- }
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- } ) ;
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-
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- // On failure, it's important to still flush and deassert CS.
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- let flush_res = self . bus . flush ( ) ;
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- let cs_res = self . cs . set_high ( ) ;
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-
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- op_res. map_err ( DeviceError :: Spi ) ?;
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- flush_res. map_err ( DeviceError :: Spi ) ?;
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- cs_res. map_err ( DeviceError :: Cs ) ?;
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-
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- Ok ( ( ) )
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+ transaction ( operations, & mut self . bus , & mut self . delay , & mut self . cs )
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}
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}
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@@ -106,7 +85,7 @@ impl<Word: Copy + 'static, BUS, CS, D> AsyncSpiDevice<Word> for ExclusiveDevice<
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where
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BUS : AsyncSpiBus < Word > ,
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CS : OutputPin ,
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- D : AsyncDelayUs ,
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+ D : AsyncDelayNs ,
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{
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#[ inline]
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async fn transaction (
@@ -122,10 +101,10 @@ where
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Operation :: Write ( buf) => self . bus . write ( buf) . await ,
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Operation :: Transfer ( read, write) => self . bus . transfer ( read, write) . await ,
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Operation :: TransferInPlace ( buf) => self . bus . transfer_in_place ( buf) . await ,
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- Operation :: DelayUs ( us ) => match self . bus . flush ( ) . await {
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+ Operation :: DelayNs ( ns ) => match self . bus . flush ( ) . await {
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Err ( e) => Err ( e) ,
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Ok ( ( ) ) => {
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- self . delay . delay_us ( * us ) . await ;
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+ self . delay . delay_ns ( * ns ) . await ;
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Ok ( ( ) )
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}
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} ,
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