Merge #34

34: mip, satp: Allow writing to these privileged registers r=laanwj a=archshift

Per the RISC-V privileged ISA, these registers should be writable.

Co-authored-by: Gui Andrade <[email protected]>

Author: bors[bot]

src/register/mip.rs

@@ -71,3 +71,30 @@ impl Mip {
 }
 
 read_csr_as!(Mip, 0x344, __read_mip);
+set!(0x344, __set_mip);
+clear!(0x344, __clear_mip);
+
+set_clear_csr!(
+    /// User Software Interrupt Pending
+    , set_usoft, clear_usoft, 1 << 0);
+set_clear_csr!(
+    /// Supervisor Software Interrupt Pending
+    , set_ssoft, clear_ssoft, 1 << 1);
+set_clear_csr!(
+    /// Machine Software Interrupt Pending
+    , set_msoft, clear_msoft, 1 << 3);
+set_clear_csr!(
+    /// User Timer Interrupt Pending
+    , set_utimer, clear_utimer, 1 << 4);
+set_clear_csr!(
+    /// Supervisor Timer Interrupt Pending
+    , set_stimer, clear_stimer, 1 << 5);
+set_clear_csr!(
+    /// Machine Timer Interrupt Pending
+    , set_mtimer, clear_mtimer, 1 << 7);
+set_clear_csr!(
+    /// User External Interrupt Pending
+    , set_uext, clear_uext, 1 << 8);
+set_clear_csr!(
+    /// Supervisor External Interrupt Pending
+    , set_sext, clear_sext, 1 << 9);

src/register/satp.rs

@@ -87,7 +87,7 @@ pub enum Mode {
 }
 
 read_csr_as!(Satp, 0x180, __read_satp);
-write_csr!(0x180, __write_satp);
+write_csr_as_usize!(0x180, __write_satp);
 
 #[inline]
 #[cfg(riscv32)]