using riscv-target with compatible MSRV

ilya-epifanov · ilya-epifanov · commit 040eb2c8053f · 2020-05-15T21:15:43.000+02:00
diff --git a/Cargo.toml b/Cargo.toml
@@ -13,7 +13,7 @@ bare-metal = ">=0.2.0,<0.2.5"
 bit_field = "0.9.0"
 
 [build-dependencies]
-riscv-target = "0.1"
+riscv-target = "0.1.2"
 
 [features]
 inline-asm = []
