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Merge #37
37: Fix _start_trap save/restore sequences r=laanwj a=Disasm Co-authored-by: Vadim Kaushan <[email protected]>
2 parents c284f35 + 6fe10d1 commit 0427294

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6 files changed

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-36
lines changed

6 files changed

+53
-36
lines changed

riscv-rt/asm.S

Lines changed: 38 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
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#include "asm.h"
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13
/*
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Entry point of all programs (_start).
35
@@ -88,45 +90,45 @@ _start:
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.global _start_trap
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_start_trap:
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addi sp, sp, -16*4
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sw ra, 0*4(sp)
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sw t0, 1*4(sp)
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sw t1, 2*4(sp)
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sw t2, 3*4(sp)
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sw t3, 4*4(sp)
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sw t4, 5*4(sp)
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sw t5, 6*4(sp)
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sw t6, 7*4(sp)
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sw a0, 8*4(sp)
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sw a1, 9*4(sp)
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sw a2, 10*4(sp)
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sw a3, 11*4(sp)
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sw a4, 12*4(sp)
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sw a5, 13*4(sp)
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sw a6, 14*4(sp)
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sw a7, 15*4(sp)
93+
addi sp, sp, -16*REGBYTES
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STORE ra, 0*REGBYTES(sp)
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STORE t0, 1*REGBYTES(sp)
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STORE t1, 2*REGBYTES(sp)
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STORE t2, 3*REGBYTES(sp)
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STORE t3, 4*REGBYTES(sp)
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STORE t4, 5*REGBYTES(sp)
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STORE t5, 6*REGBYTES(sp)
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STORE t6, 7*REGBYTES(sp)
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STORE a0, 8*REGBYTES(sp)
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STORE a1, 9*REGBYTES(sp)
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STORE a2, 10*REGBYTES(sp)
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STORE a3, 11*REGBYTES(sp)
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STORE a4, 12*REGBYTES(sp)
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STORE a5, 13*REGBYTES(sp)
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STORE a6, 14*REGBYTES(sp)
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STORE a7, 15*REGBYTES(sp)
109111

110112
jal ra, _start_trap_rust
111113

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lw ra, 0*4(sp)
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lw t0, 1*4(sp)
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lw t1, 2*4(sp)
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lw t2, 3*4(sp)
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lw t3, 4*4(sp)
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lw t4, 5*4(sp)
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lw t5, 6*4(sp)
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lw t6, 7*4(sp)
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lw a0, 8*4(sp)
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lw a1, 9*4(sp)
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lw a2, 10*4(sp)
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lw a3, 11*4(sp)
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lw a4, 12*4(sp)
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lw a5, 13*4(sp)
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lw a6, 14*4(sp)
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lw a7, 15*4(sp)
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addi sp, sp, 16*4
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LOAD ra, 0*REGBYTES(sp)
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LOAD t0, 1*REGBYTES(sp)
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LOAD t1, 2*REGBYTES(sp)
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LOAD t2, 3*REGBYTES(sp)
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LOAD t3, 4*REGBYTES(sp)
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LOAD t4, 5*REGBYTES(sp)
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LOAD t5, 6*REGBYTES(sp)
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LOAD t6, 7*REGBYTES(sp)
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LOAD a0, 8*REGBYTES(sp)
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LOAD a1, 9*REGBYTES(sp)
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LOAD a2, 10*REGBYTES(sp)
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LOAD a3, 11*REGBYTES(sp)
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LOAD a4, 12*REGBYTES(sp)
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LOAD a5, 13*REGBYTES(sp)
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LOAD a6, 14*REGBYTES(sp)
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LOAD a7, 15*REGBYTES(sp)
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131+
addi sp, sp, 16*REGBYTES
130132
mret
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132134

riscv-rt/asm.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
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#ifndef _RISCV_RT_ASM_H
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#define _RISCV_RT_ASM_H
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#if __riscv_xlen == 64
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# define STORE sd
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# define LOAD ld
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# define LOG_REGBYTES 3
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#else
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# define STORE sw
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# define LOAD lw
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# define LOG_REGBYTES 2
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#endif
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#define REGBYTES (1 << LOG_REGBYTES)
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#endif
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