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| 1 | +# Change Log |
| 2 | + |
| 3 | +All notable changes to this project will be documented in this file. |
| 4 | + |
| 5 | +The format is based on [Keep a Changelog](http://keepachangelog.com/) |
| 6 | +and this project adheres to [Semantic Versioning](http://semver.org/). |
| 7 | + |
| 8 | +## [Unreleased] |
| 9 | + |
| 10 | +### Added |
| 11 | + |
| 12 | +- New GitHub workflow for checking invalid labels in PRs |
| 13 | +- New GitHub workflow for checking modifications on CHANGELOG.md |
| 14 | +- New GitHub workflow for checking clippy lints in PRs |
| 15 | +- Optional cargo feature `single-hart` for single CPU targets |
| 16 | + |
| 17 | +### Changed |
| 18 | + |
| 19 | +- Use inline assembly instead of pre-compiled blobs |
| 20 | +- Removed bors in favor of GitHub Merge Queue |
| 21 | +- `start_trap_rust` is now marked as `unsafe` |
| 22 | +- Implement `r0` as inline assembly |
| 23 | +- Use `${ARCH_WIDTH}` in `link.x.in` to adapt to different archs |
| 24 | +- mhartid CSR is no longer read in single-hart mode, assumed zero |
| 25 | +- Ensure stack pointer is 16-byte aligned before jumping to Rust entry point |
| 26 | + |
| 27 | +## [v0.11.0] - 2023-01-18 |
| 28 | + |
| 29 | +### Changed |
| 30 | + |
| 31 | +- Update `riscv` to version 0.10.1 fixing a critical section bug |
| 32 | + |
| 33 | +## [v0.10.0] - 2022-11-04 |
| 34 | + |
| 35 | +### Added |
| 36 | + |
| 37 | +- Optional cargo feature `s-mode` for supervisor mode, including conditional compilation for supervisor/machine mode instructions. |
| 38 | + |
| 39 | +### Changed |
| 40 | + |
| 41 | +- Remove superfluous parentheses from link.x, which caused linker errors with nightly. |
| 42 | +- Changed `mp_hook` signature, hartid as passed as usize parameter by the caller (required for `s-mode` feature). |
| 43 | +- Update `riscv` to version 0.9 |
| 44 | + |
| 45 | +## [v0.9.0] - 2022-07-01 |
| 46 | + |
| 47 | +### Added |
| 48 | + |
| 49 | +- Pass `a0..a2` register values to the `#[entry]` function. |
| 50 | + |
| 51 | +### Changed |
| 52 | + |
| 53 | +- Update `riscv` to version 0.8 |
| 54 | +- Update `riscv-rt-macros` to 0.2.0 |
| 55 | +- Update Minimum Supported Rust Version to 1.59 |
| 56 | +- The main symbol is no longer randomly generated in the `#[entry]` macro, instead it uses `__risc_v_rt__main`. |
| 57 | + |
| 58 | +### Removed |
| 59 | + |
| 60 | +- Remove `inline-asm` feature which is now always enabled |
| 61 | + |
| 62 | +## [v0.8.1] - 2022-01-25 |
| 63 | + |
| 64 | +### Added |
| 65 | + |
| 66 | +- Enable float support for targets with extension sets F and D |
| 67 | +- Add ability to override trap handling mechanism |
| 68 | + |
| 69 | +### Changed |
| 70 | + |
| 71 | +- Update `riscv` to version 0.7 |
| 72 | +- Update `quote` to version 1.0 |
| 73 | +- Update `proc-macro2` to version 1.0 |
| 74 | +- Update `rand` to version to version 0.7.3 |
| 75 | + |
| 76 | +## [v0.8.0] - 2020-07-18 |
| 77 | + |
| 78 | +### Changed |
| 79 | + |
| 80 | +- Update `riscv` to version 0.6 |
| 81 | +- Update Minimum Supported Rust Version to 1.42.0 |
| 82 | + |
| 83 | +## [v0.7.2] - 2020-07-16 |
| 84 | + |
| 85 | +### Changed |
| 86 | + |
| 87 | +- Preserve `.eh_frame` and `.eh_frame_hdr` sections |
| 88 | +- Place `.srodata` and `.srodata.*` sections in `.rodata` |
| 89 | + |
| 90 | +## [v0.7.1] - 2020-06-02 |
| 91 | + |
| 92 | +### Added |
| 93 | + |
| 94 | +- Add support to initialize custom interrupt controllers. |
| 95 | + |
| 96 | +### Changed |
| 97 | + |
| 98 | +- Exception handler may return now |
| 99 | + |
| 100 | +## [v0.7.0] - 2020-03-10 |
| 101 | + |
| 102 | +### Added |
| 103 | + |
| 104 | +- Assure address of PC at startup |
| 105 | +- Implement interrupt and exception handling |
| 106 | +- Add support for the `riscv32i-unknown-none-elf` target |
| 107 | +- Added Changelog |
| 108 | + |
| 109 | +### Fixed |
| 110 | + |
| 111 | +- Fix linker script compatibility with GNU linker |
| 112 | + |
| 113 | +### Changed |
| 114 | + |
| 115 | +- Move `abort` out of the `.init` section |
| 116 | +- Update `r0` to v1.0.0 |
| 117 | +- Set MSRV to 1.38 |
| 118 | + |
| 119 | + |
| 120 | +[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.11.0..HEAD |
| 121 | +[v0.10.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.10.0...v0.11.0 |
| 122 | +[v0.10.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.9.1...v0.10.0 |
| 123 | +[v0.9.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.1...v0.9.0 |
| 124 | +[v0.8.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.8.0...v0.8.1 |
| 125 | +[v0.8.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.2...v0.8.0 |
| 126 | +[v0.7.2]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.1...v0.7.2 |
| 127 | +[v0.7.1]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.0...v0.7.1 |
| 128 | +[v0.7.0]: https://github.com/rust-embedded/riscv-rt/compare/v0.6.1...v0.7.0 |
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