riscv: define scounteren CSR with macro helpers

Uses CSR macro helpers to define the `scounteren` CSR register.

Author: rmsyn

riscv/CHANGELOG.md

@@ -35,6 +35,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use CSR helper macros to define `pmpcfgx` field types
 - Use CSR helper macros to define `scause` field types
 - Use CSR helper macros to define `sie` register
+- Use CSR helper macros to define `scounteren` field types
 
 ## [v0.12.1] - 2024-10-20
 

riscv/src/register/scounteren.rs

@@ -2,57 +2,36 @@
 
 use crate::result::{Error, Result};
 
-/// scounteren register
-#[derive(Clone, Copy, Debug)]
-pub struct Scounteren {
-    bits: usize,
+read_write_csr! {
+    /// scounteren register
+    Scounteren: 0x106,
+    mask: 0xffff_ffff,
 }
 
-impl Scounteren {
+read_write_csr_field! {
+    Scounteren,
     /// User "cycle\[h\]" Enable
-    #[inline]
-    pub fn cy(&self) -> bool {
-        self.bits & (1 << 0) != 0
-    }
+    cy: 0,
+}
 
+read_write_csr_field! {
+    Scounteren,
     /// User "time\[h\]" Enable
-    #[inline]
-    pub fn tm(&self) -> bool {
-        self.bits & (1 << 1) != 0
-    }
+    tm: 1,
+}
 
+read_write_csr_field! {
+    Scounteren,
     /// User "instret\[h]\" Enable
-    #[inline]
-    pub fn ir(&self) -> bool {
-        self.bits & (1 << 2) != 0
-    }
-
-    /// User "hpm\[x\]" Enable (bits 3-31)
-    #[inline]
-    pub fn hpm(&self, index: usize) -> bool {
-        assert!((3..32).contains(&index));
-        self.bits & (1 << index) != 0
-    }
+    ir: 2,
+}
 
+read_write_csr_field! {
+    Scounteren,
     /// User "hpm\[x\]" Enable (bits 3-31)
-    ///
-    /// Attempts to read the "hpm\[x\]" value, and returns an error if the index is invalid.
-    #[inline]
-    pub fn try_hpm(&self, index: usize) -> Result<bool> {
-        if (3..32).contains(&index) {
-            Ok(self.bits & (1 << index) != 0)
-        } else {
-            Err(Error::IndexOutOfBounds {
-                index,
-                min: 3,
-                max: 31,
-            })
-        }
-    }
+    hpm: 3..=31,
 }
 
-read_csr_as!(Scounteren, 0x106);
-write_csr!(0x106);
 set!(0x106);
 clear!(0x106);
 
@@ -68,12 +47,17 @@ set_clear_csr!(
 /// User instret Enable
     , set_ir, clear_ir, 1 << 2);
 
+/// Sets the "hpm\[x\]" enable (bits 3-31).
+///
+/// # Note
+///
+/// Panics if `index` is out-of-bounds.
 #[inline]
 pub unsafe fn set_hpm(index: usize) {
-    assert!((3..32).contains(&index));
-    _set(1 << index);
+    try_set_hpm(index).unwrap();
 }
 
+/// Attempts to set the "hpm\[x\]" enable (bits 3-31).
 #[inline]
 pub unsafe fn try_set_hpm(index: usize) -> Result<()> {
     if (3..32).contains(&index) {
@@ -87,12 +71,17 @@ pub unsafe fn try_set_hpm(index: usize) -> Result<()> {
     }
 }
 
+/// Clears the "hpm\[x\]" enable (bits 3-31).
+///
+/// # Note
+///
+/// Panics if `index` is out-of-bounds.
 #[inline]
 pub unsafe fn clear_hpm(index: usize) {
-    assert!((3..32).contains(&index));
-    _clear(1 << index);
+    try_clear_hpm(index).unwrap()
 }
 
+/// Attempts to clear the "hpm\[x\]" enable (bits 3-31).
 #[inline]
 pub unsafe fn try_clear_hpm(index: usize) -> Result<()> {
     if (3..32).contains(&index) {