We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 8baa254 commit 1241212Copy full SHA for 1241212
riscv-rt/src/asm.rs
@@ -184,12 +184,16 @@ cfg_global_asm!(
184
// INITIALIZE FLOATING POINT UNIT
185
#[cfg(any(riscvf, riscvd))]
186
cfg_global_asm!(
187
+ "
188
+ li t0, 0x4000 // bit 14 is FS most significant bit
189
+ li t2, 0x2000 // bit 13 is FS least significant bit
190
+ ",
191
#[cfg(feature = "s-mode")]
- "csrrc x0, sstatus, 0x4000
- csrrs x0, sstatus, 0x2000",
192
+ "csrrc x0, sstatus, t0
193
+ csrrs x0, sstatus, t2",
194
#[cfg(not(feature = "s-mode"))]
- "csrrc x0, mstatus, 0x4000
- csrrs x0, mstatus, 0x2000",
195
+ "csrrc x0, mstatus, t0
196
+ csrrs x0, mstatus, t2",
197
"fscsr x0",
198
);
199
// ZERO OUT FLOATING POINT REGISTERS
0 commit comments