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Utility functions now only in macros
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6 files changed

+89
-176
lines changed

6 files changed

+89
-176
lines changed

‎src/aclint.rs

Lines changed: 0 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -65,77 +65,13 @@ impl<C: Clint> CLINT<C> {
6565

6666
const MTIME_OFFSET: usize = 0xBFF8;
6767

68-
/// Returns `true` if any CLINT-related interrupt is pending.
69-
#[inline]
70-
pub fn is_interrupting() -> bool {
71-
Self::mswi_is_interrupting() || Self::mtimer_is_interrupting()
72-
}
73-
74-
/// Returns `true` if a machine software interrupt is pending.
75-
#[inline]
76-
pub fn mswi_is_interrupting() -> bool {
77-
mswi::MSWI::is_interrupting()
78-
}
79-
80-
/// Returns `true` if Machine Software Interrupts are enabled.
81-
/// This bit must be set for the `MSWI` to trigger machine software interrupts.
82-
#[inline]
83-
pub fn mswi_is_enabled() -> bool {
84-
mswi::MSWI::is_enabled()
85-
}
86-
87-
/// Enables machine software interrupts to let the `MSWI` peripheral trigger interrupts.
88-
///
89-
/// # Safety
90-
///
91-
/// Enabling the `MSWI` may break mask-based critical sections.
92-
#[inline]
93-
pub unsafe fn mswi_enable() {
94-
mswi::MSWI::enable();
95-
}
96-
97-
/// Disables machine software interrupts to prevent the `MSWI` peripheral from triggering interrupts.
98-
#[inline]
99-
pub fn mswi_disable() {
100-
mswi::MSWI::disable();
101-
}
102-
10368
/// Returns the `MSWI` peripheral.
10469
#[inline]
10570
pub const fn mswi() -> mswi::MSWI {
10671
// SAFETY: valid base address
10772
unsafe { mswi::MSWI::new(C::BASE) }
10873
}
10974

110-
/// Returns `true` if a machine timer interrupt is pending.
111-
#[inline]
112-
pub fn mtimer_is_interrupting() -> bool {
113-
mtimer::MTIMER::is_interrupting()
114-
}
115-
116-
/// Returns `true` if Machine Timer Interrupts are enabled.
117-
/// This bit must be set for the `MTIMER` to trigger machine timer interrupts.
118-
#[inline]
119-
pub fn mtimer_is_enabled() -> bool {
120-
mtimer::MTIMER::is_enabled()
121-
}
122-
123-
/// Enables machine timer interrupts to let the `MTIMER` peripheral trigger interrupts.
124-
///
125-
/// # Safety
126-
///
127-
/// Enabling the `MTIMER` may break mask-based critical sections.
128-
#[inline]
129-
pub unsafe fn mtimer_enable() {
130-
mtimer::MTIMER::enable();
131-
}
132-
133-
/// Disables machine timer interrupts to prevent the `MTIMER` peripheral from triggering interrupts.
134-
#[inline]
135-
pub fn mtimer_disable() {
136-
mtimer::MTIMER::disable();
137-
}
138-
13975
/// Returns the `MTIMER` peripheral.
14076
#[inline]
14177
pub const fn mtimer() -> mtimer::MTIMER {

‎src/aclint/mswi.rs

Lines changed: 0 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -25,37 +25,6 @@ impl MSWI {
2525
}
2626
}
2727

28-
/// Returns `true` if a machine software interrupt is pending.
29-
#[inline]
30-
pub fn is_interrupting() -> bool {
31-
riscv::register::mip::read().msoft()
32-
}
33-
34-
/// Returns `true` if Machine Software Interrupts are enabled.
35-
#[inline]
36-
pub fn is_enabled() -> bool {
37-
riscv::register::mie::read().msoft()
38-
}
39-
40-
/// Sets the Machine Software Interrupt bit of the `mie` CSR.
41-
/// This bit must be set for the `MSWI` to trigger machine software interrupts.
42-
///
43-
/// # Safety
44-
///
45-
/// Enabling the `MSWI` may break mask-based critical sections.
46-
#[inline]
47-
pub unsafe fn enable() {
48-
riscv::register::mie::set_msoft();
49-
}
50-
51-
/// Clears the Machine Software Interrupt bit of the `mie` CSR.
52-
/// When cleared, the `MSWI` cannot trigger machine software interrupts.
53-
#[inline]
54-
pub fn disable() {
55-
// SAFETY: it is safe to disable interrupts
56-
unsafe { riscv::register::mie::clear_msoft() };
57-
}
58-
5928
/// Returns the `MSIP` register for the HART which ID is `hart_id`.
6029
///
6130
/// # Note

‎src/aclint/mtimer.rs

Lines changed: 0 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -27,37 +27,6 @@ impl MTIMER {
2727
}
2828
}
2929

30-
/// Returns `true` if a machine timer interrupt is pending.
31-
#[inline]
32-
pub fn is_interrupting() -> bool {
33-
riscv::register::mip::read().mtimer()
34-
}
35-
36-
/// Returns `true` if Machine Timer Interrupts are enabled.
37-
#[inline]
38-
pub fn is_enabled() -> bool {
39-
riscv::register::mie::read().mtimer()
40-
}
41-
42-
/// Sets the Machine Timer Interrupt bit of the `mie` CSR.
43-
/// This bit must be set for the `MTIMER` to trigger machine timer interrupts.
44-
///
45-
/// # Safety
46-
///
47-
/// Enabling the `MTIMER` may break mask-based critical sections.
48-
#[inline]
49-
pub unsafe fn enable() {
50-
riscv::register::mie::set_mtimer();
51-
}
52-
53-
/// Clears the Machine Timer Interrupt bit of the `mie` CSR.
54-
/// When cleared, the `MTIMER` cannot trigger machine timer interrupts.
55-
#[inline]
56-
pub fn disable() {
57-
// SAFETY: it is safe to disable interrupts
58-
unsafe { riscv::register::mie::clear_mtimer() };
59-
}
60-
6130
/// Returns the `MTIMECMP` register for the HART which ID is `hart_id`.
6231
///
6332
/// # Note

‎src/lib.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,10 @@
33
#![deny(missing_docs)]
44
#![no_std]
55

6-
pub use riscv; // re-export riscv crate to allow users to use it without importing it
6+
pub use riscv; // re-export riscv crate to allow macros to use it
77

8-
pub mod common;
8+
pub mod common; // common definitions for all peripherals
99
pub mod macros; // macros for easing the definition of peripherals in PACs
1010

11-
pub mod aclint;
12-
pub mod plic;
11+
pub mod aclint; // ACLINT and CLINT peripherals
12+
pub mod plic; // PLIC peripheral

‎src/macros.rs

Lines changed: 85 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -75,42 +75,99 @@ macro_rules! clint_codegen {
7575
}
7676

7777
impl CLINT {
78+
/// Returns `true` if a machine timer **OR** software interrupt is pending.
79+
#[inline]
80+
pub fn is_interrupting() -> bool {
81+
Self::mswi_is_interrupting() || Self::mtimer_is_interrupting()
82+
}
83+
84+
/// Returns `true` if machine timer **OR** software interrupts are enabled.
85+
pub fn is_enabled() -> bool {
86+
Self::mswi_is_enabled() || Self::mtimer_is_enabled()
87+
}
88+
89+
/// Enables machine timer **AND** software interrupts to allow the CLINT to trigger interrupts.
90+
///
91+
/// # Safety
92+
///
93+
/// Enabling the `CLINT` may break mask-based critical sections.
94+
#[inline]
95+
pub unsafe fn enable() {
96+
Self::mswi_enable();
97+
Self::mtimer_enable();
98+
}
99+
100+
/// Disables machine timer **AND** software interrupts to prevent the CLINT from triggering interrupts.
101+
#[inline]
102+
pub fn disable() {
103+
Self::mswi_disable();
104+
Self::mtimer_disable();
105+
}
106+
107+
/// Returns `true` if a machine software interrupt is pending.
108+
#[inline]
109+
pub fn mswi_is_interrupting() -> bool {
110+
$crate::riscv::register::mip::read().msoft()
111+
}
112+
113+
/// Returns `true` if Machine Software Interrupts are enabled.
114+
#[inline]
115+
pub fn mswi_is_enabled() -> bool {
116+
$crate::riscv::register::mie::read().msoft()
117+
}
118+
78119
/// Enables the `MSWI` peripheral.
79120
///
80121
/// # Safety
81122
///
82123
/// Enabling the `MSWI` may break mask-based critical sections.
83124
#[inline]
84125
pub unsafe fn mswi_enable() {
85-
$crate::aclint::CLINT::<CLINT>::mswi_enable();
126+
$crate::riscv::register::mie::set_msoft();
86127
}
87128

88129
/// Disables the `MSWI` peripheral.
89130
#[inline]
90131
pub fn mswi_disable() {
91-
$crate::aclint::CLINT::<CLINT>::mswi_disable();
132+
// SAFETY: it is safe to disable interrupts
133+
unsafe { $crate::riscv::register::mie::clear_msoft() };
134+
}
135+
136+
/// Returns the `MSWI` peripheral.
137+
#[inline]
138+
pub const fn mswi() -> $crate::aclint::mswi::MSWI {
139+
$crate::aclint::CLINT::<CLINT>::mswi()
140+
}
141+
142+
/// Returns `true` if a machine timer interrupt is pending.
143+
#[inline]
144+
pub fn mtimer_is_interrupting() -> bool {
145+
$crate::riscv::register::mip::read().mtimer()
146+
}
147+
148+
/// Returns `true` if Machine Timer Interrupts are enabled.
149+
#[inline]
150+
pub fn mtimer_is_enabled() -> bool {
151+
$crate::riscv::register::mie::read().mtimer()
92152
}
93153

94-
/// Enables the `MTIMER` peripheral.
154+
/// Sets the Machine Timer Interrupt bit of the `mie` CSR.
155+
/// This bit must be set for the `MTIMER` to trigger machine timer interrupts.
95156
///
96157
/// # Safety
97158
///
98159
/// Enabling the `MTIMER` may break mask-based critical sections.
99160
#[inline]
100161
pub unsafe fn mtimer_enable() {
101-
$crate::aclint::CLINT::<CLINT>::mtimer_enable();
162+
$crate::riscv::register::mie::set_mtimer();
102163
}
103164

104-
/// Disables the `MTIMER` peripheral.
165+
/// Clears the Machine Timer Interrupt bit of the `mie` CSR.
166+
/// When cleared, the `MTIMER` cannot trigger machine timer interrupts.
105167
#[inline]
106-
pub fn disable_mtimer() {
107-
$crate::aclint::CLINT::<CLINT>::mtimer_disable();
108-
}
109-
110-
/// Returns the `MSWI` peripheral.
111-
#[inline]
112-
pub const fn mswi() -> $crate::aclint::mswi::MSWI {
113-
$crate::aclint::CLINT::<CLINT>::mswi()
168+
pub fn mtimer_disable() {
169+
// SAFETY: it is safe to disable interrupts
170+
unsafe { $crate::riscv::register::mie::clear_mtimer() };
114171
}
115172

116173
/// Returns the `MTIMER` peripheral.
@@ -154,20 +211,33 @@ macro_rules! plic_codegen {
154211
}
155212

156213
impl PLIC {
214+
/// Returns `true` if a machine external interrupt is pending.
215+
#[inline]
216+
pub fn is_interrupting() -> bool {
217+
$crate::riscv::register::mip::read().mext()
218+
}
219+
220+
/// Returns true if Machine External Interrupts are enabled.
221+
#[inline]
222+
pub fn is_enabled() -> bool {
223+
$crate::riscv::register::mie::read().mext()
224+
}
225+
157226
/// Enables machine external interrupts to allow the PLIC to trigger interrupts.
158227
///
159228
/// # Safety
160229
///
161230
/// Enabling the `PLIC` may break mask-based critical sections.
162231
#[inline]
163232
pub unsafe fn enable() {
164-
$crate::plic::PLIC::<PLIC>::enable();
233+
$crate::riscv::register::mie::set_mext();
165234
}
166235

167236
/// Disables machine external interrupts to prevent the PLIC from triggering interrupts.
168237
#[inline]
169238
pub fn disable() {
170-
$crate::plic::PLIC::<PLIC>::disable();
239+
// SAFETY: it is safe to disable interrupts
240+
unsafe { $crate::riscv::register::mie::clear_mext() };
171241
}
172242

173243
/// Returns the priorities register of the PLIC.

‎src/plic.rs

Lines changed: 0 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -127,37 +127,6 @@ impl<P: Plic> PLIC<P> {
127127

128128
const PENDINGS_OFFSET: usize = 0x1000;
129129

130-
/// Returns `true` if a machine external interrupt is pending.
131-
#[inline]
132-
pub fn is_interrupting() -> bool {
133-
riscv::register::mip::read().mext()
134-
}
135-
136-
/// Returns true if Machine External Interrupts are enabled.
137-
#[inline]
138-
pub fn is_enabled() -> bool {
139-
riscv::register::mie::read().mext()
140-
}
141-
142-
/// Sets the Machine External Interrupt bit of the `mie` CSR.
143-
/// This bit must be set for the PLIC to trigger machine external interrupts.
144-
///
145-
/// # Safety
146-
///
147-
/// Enabling the `PLIC` may break mask-based critical sections.
148-
#[inline]
149-
pub unsafe fn enable() {
150-
riscv::register::mie::set_mext();
151-
}
152-
153-
/// Clears the Machine External Interrupt bit of the `mie` CSR.
154-
/// When cleared, the PLIC does not trigger machine external interrupts.
155-
#[inline]
156-
pub fn disable() {
157-
// SAFETY: it is safe to disable interrupts
158-
unsafe { riscv::register::mie::clear_mext() };
159-
}
160-
161130
/// Returns the priorities register of the PLIC.
162131
/// This register allows to set the priority level of each interrupt source.
163132
/// The priority level of each interrupt source is shared among all the contexts.

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