fix cargo fmt

Author: almindor

build.rs

@@ -13,12 +13,13 @@ fn main() {
         let mut target = Target::from_target_str(&target);
         target.retain_extensions("ic");
 
-        let target = target.to_string();    
+        let target = target.to_string();
 
         fs::copy(
             format!("bin/{}.a", target),
             out_dir.join(format!("lib{}.a", name)),
-        ).unwrap();
+        )
+        .unwrap();
 
         println!("cargo:rustc-link-lib=static={}", name);
         println!("cargo:rustc-link-search={}", out_dir.display());

src/asm.rs

@@ -25,7 +25,6 @@ macro_rules! instruction {
     )
 }
 
-
 instruction!(
     /// `EBREAK` instruction wrapper
     ///
@@ -47,7 +46,6 @@ instruction!(
     /// `SFENCE.VMA` are ordered before all implicit references subsequent to the `SFENCE.VMA`.
     , sfence_vma_all, "sfence.vma", __sfence_vma_all);
 
-
 /// `SFENCE.VMA` instruction wrapper
 ///
 /// Synchronizes updates to in-memory memory-management data structures with current execution.

src/interrupt.rs

@@ -40,14 +40,18 @@ where
     let mstatus = mstatus::read();
 
     // disable interrupts
-    unsafe { disable(); }
+    unsafe {
+        disable();
+    }
 
     let r = f(unsafe { &CriticalSection::new() });
 
     // If the interrupts were active before our `disable` call, then re-enable
     // them. Otherwise, keep them disabled
     if mstatus.mie() {
-        unsafe { enable(); }
+        unsafe {
+            enable();
+        }
     }
 
     r

src/register/fcsr.rs

@@ -107,7 +107,9 @@ clear!(0x003, __clear_fcsr);
 /// Reads the CSR
 #[inline]
 pub fn read() -> FCSR {
-    FCSR { bits: unsafe{ _read() as u32 } }
+    FCSR {
+        bits: unsafe { _read() as u32 },
+    }
 }
 
 /// Writes the CSR

src/register/macros.rs

@@ -63,7 +63,9 @@ macro_rules! read_csr_as {
         /// Reads the CSR
         #[inline]
         pub fn read() -> $register {
-            $register { bits: unsafe{ _read() } }
+            $register {
+                bits: unsafe { _read() },
+            }
         }
     };
 }
@@ -75,7 +77,7 @@ macro_rules! read_csr_as_usize {
         /// Reads the CSR
         #[inline]
         pub fn read() -> usize {
-            unsafe{ _read() }
+            unsafe { _read() }
         }
     };
 }
@@ -87,7 +89,7 @@ macro_rules! read_csr_as_usize_rv32 {
         /// Reads the CSR
         #[inline]
         pub fn read() -> usize {
-            unsafe{ _read() }
+            unsafe { _read() }
         }
     };
 }
@@ -151,7 +153,7 @@ macro_rules! write_csr_as_usize {
         /// Writes the CSR
         #[inline]
         pub fn write(bits: usize) {
-            unsafe{ _write(bits) }
+            unsafe { _write(bits) }
         }
     };
 }
@@ -163,7 +165,7 @@ macro_rules! write_csr_as_usize_rv32 {
         /// Writes the CSR
         #[inline]
         pub fn write(bits: usize) {
-            unsafe{ _write(bits) }
+            unsafe { _write(bits) }
         }
     };
 }
@@ -266,5 +268,5 @@ macro_rules! read_composite_csr {
                 () => $lo as u64,
             }
         }
-    }
+    };
 }

src/register/marchid.rs

@@ -20,7 +20,7 @@ read_csr!(0xF11, __read_marchid);
 /// Reads the CSR
 #[inline]
 pub fn read() -> Option<Marchid> {
-    let r = unsafe{ _read() };
+    let r = unsafe { _read() };
     // When marchid is hardwired to zero it means that the marchid
     // csr isn't implemented.
     NonZeroUsize::new(r).map(|bits| Marchid { bits })

src/register/mcause.rs

@@ -65,7 +65,6 @@ impl Interrupt {
     }
 }
 
-
 impl Exception {
     pub fn from(nr: usize) -> Self {
         match nr {

src/register/mhpmeventx.rs

@@ -7,16 +7,16 @@ macro_rules! reg {
             read_csr_as_usize!($addr, $readf);
             write_csr_as_usize!($addr, $writef);
         }
-    }
+    };
 }
 
-reg!(0x323, mhpmevent3,  __read_mhpmevent3,  __write_mhpmevent3);
-reg!(0x324, mhpmevent4,  __read_mhpmevent4,  __write_mhpmevent4);
-reg!(0x325, mhpmevent5,  __read_mhpmevent5,  __write_mhpmevent5);
-reg!(0x326, mhpmevent6,  __read_mhpmevent6,  __write_mhpmevent6);
-reg!(0x327, mhpmevent7,  __read_mhpmevent7,  __write_mhpmevent7);
-reg!(0x328, mhpmevent8,  __read_mhpmevent8,  __write_mhpmevent8);
-reg!(0x329, mhpmevent9,  __read_mhpmevent9,  __write_mhpmevent9);
+reg!(0x323, mhpmevent3, __read_mhpmevent3, __write_mhpmevent3);
+reg!(0x324, mhpmevent4, __read_mhpmevent4, __write_mhpmevent4);
+reg!(0x325, mhpmevent5, __read_mhpmevent5, __write_mhpmevent5);
+reg!(0x326, mhpmevent6, __read_mhpmevent6, __write_mhpmevent6);
+reg!(0x327, mhpmevent7, __read_mhpmevent7, __write_mhpmevent7);
+reg!(0x328, mhpmevent8, __read_mhpmevent8, __write_mhpmevent8);
+reg!(0x329, mhpmevent9, __read_mhpmevent9, __write_mhpmevent9);
 reg!(0x32A, mhpmevent10, __read_mhpmevent10, __write_mhpmevent10);
 reg!(0x32B, mhpmevent11, __read_mhpmevent11, __write_mhpmevent11);
 reg!(0x32C, mhpmevent12, __read_mhpmevent12, __write_mhpmevent12);

src/register/mimpid.rs

@@ -20,7 +20,7 @@ read_csr!(0xF11, __read_mimpid);
 /// Reads the CSR
 #[inline]
 pub fn read() -> Option<Mimpid> {
-    let r = unsafe{ _read() };
+    let r = unsafe { _read() };
     // When mimpid is hardwired to zero it means that the mimpid
     // csr isn't implemented.
     NonZeroUsize::new(r).map(|bits| Mimpid { bits })

src/register/misa.rs

@@ -53,7 +53,7 @@ read_csr!(0x301, __read_misa);
 /// Reads the CSR
 #[inline]
 pub fn read() -> Option<Misa> {
-    let r = unsafe{ _read() };
+    let r = unsafe { _read() };
     // When misa is hardwired to zero it means that the misa csr
     // isn't implemented.
     NonZeroUsize::new(r).map(|bits| Misa { bits })