MSRV is now 1.75

Author: romancardenas

.github/workflows/riscv-peripheral.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.61.0
-        toolchain: [ stable, nightly, 1.61.0 ]
+        # All generated code should be running on stable now, MRSV is 1.75.0
+        toolchain: [ stable, nightly, 1.75.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf
@@ -33,9 +33,8 @@ jobs:
         targets: ${{ matrix.target }}
     - name: Build (no features)
       run: cargo build --package riscv-peripheral --target ${{ matrix.target }}
-    # not yet, let's wait for 1.75.0
-    # - name: Build (all features)
-    #  run: cargo build --package riscv-peripheral --target ${{ matrix.target }} --all-features
+    - name: Build (all features)
+      run: cargo build --package riscv-peripheral --target ${{ matrix.target }} --all-features
 
   # On MacOS, Ubuntu, and Windows, we run the tests.
   build-others:
@@ -48,9 +47,8 @@ jobs:
       - uses: dtolnay/rust-toolchain@stable
       - name: Build (no features)
         run: cargo test --package riscv-peripheral
-      # not yet, let's wait for 1.75.0
-      # - name: Build (all features)
-      #  run: cargo test --package riscv-peripheral --all-features
+      - name: Build (all features)
+        run: cargo test --package riscv-peripheral --all-features
 
   # Job to check that all the builds succeeded
   build-check:

riscv-pac/CHANGELOG.md

@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Fix crates.io badge links
+
 ## [v0.1.0] - 2024-01-14
 
 ### Added

riscv-pac/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv-pac"
-version = "0.1.0"
+version = "0.1.1"
 edition = "2021"
 rust-version = "1.60"
 repository = "https://github.com/rust-embedded/riscv"

riscv-pac/README.md

@@ -16,7 +16,7 @@ compile with older versions but that may change in any new patch release.
 
 ## License
 
-Copyright 2023-2024s [RISC-V team][team]
+Copyright 2023-2024 [RISC-V team][team]
 
 Permission to use, copy, modify, and/or distribute this software for any purpose
 with or without fee is hereby granted, provided that the above copyright notice

riscv-peripheral/Cargo.toml

@@ -8,7 +8,7 @@ edition = "2021"
 [dependencies]
 embedded-hal = "1.0.0"
 embedded-hal-async = { version = "1.0.0", optional =  true }
-riscv = { path = "../riscv", version = "0.10" }
+riscv = { path = "../riscv", version = "0.11.0" }
 riscv-pac = { path = "../riscv-pac", version = "0.1.0" }
 
 [features]

riscv-peripheral/README.md

@@ -11,12 +11,12 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.61 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.75 and up. It *might*
 compile with older versions but that may change in any new patch release.
 
 ## License
 
-Copyright 2023-2024s [RISC-V team][team]
+Copyright 2023-2024 [RISC-V team][team]
 
 Permission to use, copy, modify, and/or distribute this software for any purpose
 with or without fee is hereby granted, provided that the above copyright notice

riscv-peripheral/src/hal_async/aclint.rs

@@ -29,11 +29,11 @@ use core::{
 
 extern "Rust" {
     /// Returns the `MTIMER` register for the given HART ID.
-    /// This is necessary for [`MachineExternal`] to obtain the corresponding `MTIMER` register.
+    /// This is necessary for [`MachineTimer`] to obtain the corresponding `MTIMER` register.
     ///
     /// # Safety
     ///
-    /// Do not call this function directly. It is only meant to be called by [`MachineExternal`].
+    /// Do not call this function directly. It is only meant to be called by [`MachineTimer`].
     fn _riscv_peripheral_aclint_mtimer(hart_id: usize) -> MTIMER;
 
     /// Tries to push a new timer to the timer queue assigned to the given HART ID.
@@ -51,15 +51,15 @@ extern "Rust" {
     ///
     /// # Safety
     ///
-    /// Do not call this function directly. It is only meant to be called by [`MachineExternal`] and [`DelayAsync`].
+    /// Do not call this function directly. It is only meant to be called by [`MachineTimer`] and [`DelayAsync`].
     fn _riscv_peripheral_aclint_wake_timers(hart_id: usize, current_tick: u64) -> Option<u64>;
 }
 
 /// Machine-level timer interrupt handler. This handler is triggered whenever the `MTIME`
 /// register reaches the value of the `MTIMECMP` register of the current HART.
 #[no_mangle]
 #[allow(non_snake_case)]
-fn MachineExternal() {
+fn MachineTimer() {
     // recover the MTIME and MTIMECMP registers for the current HART
     let hart_id = riscv::register::mhartid::read();
     let mtimer = unsafe { _riscv_peripheral_aclint_mtimer(hart_id) };