Make Xip fields read-only

Author: romancardenas

riscv/CHANGELOG.md

@@ -16,6 +16,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - New methods and functions for dealing with pending interrupts in `mip` and `sip` registers
   using the `riscv_pac::CoreInterruptNumber` trait.
 - New `riscv::interrupt::is_interrupt_pending` function.
+- New `riscv::register::xip::clear_pending` atomic function for `mip` and `sip` registers.
+  This function is marked as `unsafe`, as its availability depends both on the target chip
+  and the target interrupt source.
 
 ### Changed
 
@@ -27,6 +30,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Removed
 
 - Removed custom build script, as `cfg(riscv)` is no longer necessary.
+- All the fields of `Mip` and `Sip` CSR proxies are now read-only. This change is motivated
+  to avoid clearing unwanted interrupts triggered between CSR reads and CSR writes.
 
 ## [v0.14.0] - 2025-06-10
 

riscv/src/register/mip.rs

@@ -1,15 +1,15 @@
 //! mip register
 
-use crate::bits::{bf_extract, bf_insert};
+use crate::bits::bf_extract;
 use riscv_pac::CoreInterruptNumber;
 
-read_write_csr! {
+read_only_csr! {
     /// `mip` register
     Mip: 0x344,
     mask: usize::MAX,
 }
 
-read_write_csr_field! {
+read_only_csr_field! {
     Mip,
     /// Supervisor Software Interrupt Pending
     ssoft: 1,
@@ -21,7 +21,7 @@ read_only_csr_field! {
     msoft: 3,
 }
 
-read_write_csr_field! {
+read_only_csr_field! {
     Mip,
     /// Supervisor Timer Interrupt Pending
     stimer: 5,
@@ -33,7 +33,7 @@ read_only_csr_field! {
     mtimer: 7,
 }
 
-read_write_csr_field! {
+read_only_csr_field! {
     Mip,
     /// Supervisor External Interrupt Pending
     sext: 9,
@@ -51,18 +51,6 @@ impl Mip {
     pub fn is_pending<I: CoreInterruptNumber>(&self, interrupt: I) -> bool {
         bf_extract(self.bits, interrupt.number(), 1) != 0
     }
-
-    /// Clear the pending state of a specific core interrupt source.
-    ///
-    /// # Safety
-    ///
-    /// Not all interrupt sources allow clearing of pending interrupts via the `mip` register.
-    /// Instead, it may be necessary to perform an alternative action to clear the interrupt.
-    /// Check the specification of your target chip for details.
-    #[inline]
-    pub unsafe fn clear_pending<I: CoreInterruptNumber>(&mut self, interrupt: I) {
-        self.bits = bf_insert(self.bits, interrupt.number(), 1, 0);
-    }
 }
 
 set!(0x344);
@@ -85,6 +73,7 @@ set_clear_csr!(
 /// Not all interrupt sources allow clearing of pending interrupts via the `mip` register.
 /// Instead, it may be necessary to perform an alternative action to clear the interrupt.
 /// Check the specification of your target chip for details.
+#[inline]
 pub unsafe fn clear_pending<I: CoreInterruptNumber>(interrupt: I) {
     _clear(1 << interrupt.number());
 }

riscv/src/register/sip.rs

@@ -1,15 +1,15 @@
 //! sip register
 
-use crate::bits::{bf_extract, bf_insert};
+use crate::bits::bf_extract;
 use riscv_pac::CoreInterruptNumber;
 
-read_write_csr! {
+read_only_csr! {
     /// sip register
     Sip: 0x144,
     mask: usize::MAX,
 }
 
-read_write_csr_field! {
+read_only_csr_field! {
     Sip,
     /// Supervisor Software Interrupt Pending
     ssoft: 1,
@@ -33,18 +33,6 @@ impl Sip {
     pub fn is_pending<I: CoreInterruptNumber>(&self, interrupt: I) -> bool {
         bf_extract(self.bits, interrupt.number(), 1) != 0
     }
-
-    /// Clear the pending state of a specific core interrupt source.
-    ///
-    /// # Safety
-    ///
-    /// Not all interrupt sources allow clearing of pending interrupts via the `sip` register.
-    /// Instead, it may be necessary to perform an alternative action to clear the interrupt.
-    /// Check the specification of your target chip for details.
-    #[inline]
-    pub unsafe fn clear_pending<I: CoreInterruptNumber>(&mut self, interrupt: I) {
-        self.bits = bf_insert(self.bits, interrupt.number(), 1, 0);
-    }
 }
 
 set!(0x144);
@@ -61,6 +49,7 @@ set_clear_csr!(
 /// Not all interrupt sources allow clearing of pending interrupts via the `sip` register.
 /// Instead, it may be necessary to perform an alternative action to clear the interrupt.
 /// Check the specification of your specific core for details.
+#[inline]
 pub unsafe fn clear_pending<I: CoreInterruptNumber>(interrupt: I) {
     _clear(1 << interrupt.number());
 }