Merge #30

30: add riscv32i target r=Disasm a=sbourdeauducq

This adds support for the simplest RISC-V processor possible, which is useful e.g. for experimenting with  FPGA softcore implementations.

Co-authored-by: Sebastien Bourdeauducq <[email protected]>

Author: bors[bot]

assemble.sh

@@ -7,6 +7,9 @@ crate=riscv
 # remove existing blobs because otherwise this will append object files to the old blobs
 rm -f bin/*.a
 
+riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
+ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
+
 riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imc asm.S -o bin/$crate.o
 ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
 ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o