Merge #95

95: Pass a0..a2 to main() r=almindor a=Disasm

This PR delivers arguments stored in a0..a2 to `main`.

Fixes rust-embedded/riscv-rt#92

Tested with:
* build the `empty` example for `riscv64imac-unknown-none-elf` with a memory file which puts everything to `0x80000000`
* run `qemu-system-riscv64 -nographic -machine virt -bios target/riscv64imac-unknown-none-elf/release/examples/empty -s -S`
* connect to qemu with gdb (`target remote :1234`)
* set breakpoint to main (`b main`)
* resume execution (`continue`)
* inspect registers (`info registers`)
```
a0             0x0	0
a1             0x87000000	2264924160
a2             0x1028	4136
```
* check header (`x/xw 0x87000000`)
```
0x87000000:	0xedfe0dd0
```

Co-authored-by: Vadim Kaushan <[email protected]>

Author: bors[bot]

riscv-rt/Cargo.toml

@@ -12,7 +12,7 @@ license = "ISC"
 [dependencies]
 r0 = "1.0.0"
 riscv = "0.8"
-riscv-rt-macros = { path = "macros", version = "0.1.6" }
+riscv-rt-macros = { path = "macros", version = "0.2.0" }
 
 [dev-dependencies]
 panic-halt = "0.2.0"

riscv-rt/asm.S

@@ -58,9 +58,7 @@ _abs_start:
     li  x7, 0
     li  x8, 0
     li  x9, 0
-    li  x10,0
-    li  x11,0
-    li  x12,0
+    // a0..a2 (x10..x12) skipped
     li  x13,0
     li  x14,0
     li  x15,0
@@ -87,23 +85,23 @@ _abs_start:
     .option pop
 
     // Check hart id
-    csrr a2, mhartid
+    csrr t2, mhartid
     lui t0, %hi(_max_hart_id)
     add t0, t0, %lo(_max_hart_id)
-    bgtu a2, t0, abort
+    bgtu t2, t0, abort
 
     // Allocate stacks
     la sp, _stack_start
     lui t0, %hi(_hart_stack_size)
     add t0, t0, %lo(_hart_stack_size)
 #ifdef __riscv_mul
-    mul t0, a2, t0
+    mul t0, t2, t0
 #else
-    beqz a2, 2f  // Jump if single-hart
-    mv t1, a2
-    mv t2, t0
+    beqz t2, 2f  // Jump if single-hart
+    mv t1, t2
+    mv t3, t0
 1:
-    add t0, t0, t2
+    add t0, t0, t3
     addi t1, t1, -1
     bnez t1, 1b
 2: