Merge #102

102: Prepare v0.8.0 release r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <[email protected]>

Author: bors[bot]

CHANGELOG.md

@@ -6,11 +6,16 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/)
 and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
+
+## [v0.8.0] - 2022-04-20
+
 ### Added
+
 - Add `#[cfg(riscv32)]` to `pmpcfg1` and `pmpcfg3` modules
 - Add enums `Range`, `Permission` for PMP configuration
 - Add `set_pmp()` and `clear_pmp()` functions to pmpcfg(x) modules
 - Add struct `Pmpcsr` and is returned from `pmpcfgx::read()`
+- Add `singleton!` macro
 - Add delay structure and methods using embedded-hal traits and `mcycle` register
 - Add `asm::delay()` function for assembly-based busy-loops
 - Add `asm::nop()`, a wrapper for implementing a `nop` instruction
@@ -23,6 +28,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Inline assembly is now always used
 - Update Minimum Supported Rust Version to 1.59
 
+### Fixed
+
+- Fix `sfence.vma` operand order
+
 ### Removed
 
 - Remove `inline-asm` feature which is now always enabled
@@ -76,7 +85,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Fixed MSRV by restricting the upper bound of `bare-metal` version
 
-[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.7.0...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.8.0...HEAD
+[v0.8.0]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.8.0
 [v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.0...v0.7.0
 [v0.6.0]: https://github.com/rust-embedded/riscv/compare/v0.5.6...v0.6.0
 [v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv"
-version = "0.7.0"
+version = "0.8.0"
 rust-version = "1.59"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <[email protected]>"]