Push all the changes together

Author: romancardenas

.github/workflows/riscv-rt.yaml

@@ -42,7 +42,7 @@ jobs:
       - name : Build (v-trap)
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=v-trap
       - name: Build (all features)
-        run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --all-features
+        run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=s-mode,single-hart,v-trap
 
   # Job to check that all the builds succeeded
   build-check:

.github/workflows/riscv-semihosting.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.60.0
-        toolchain: [ stable, nightly, 1.60.0 ]
+        # All generated code should be running on stable now, MRSV is 1.61.0
+        toolchain: [ stable, nightly, 1.61.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

.github/workflows/riscv.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.60.0
-        toolchain: [ stable, nightly, 1.60.0 ]
+        # All generated code should be running on stable now, MRSV is 1.61.0
+        toolchain: [ stable, nightly, 1.61.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

riscv-peripheral/Cargo.toml

@@ -16,7 +16,7 @@ license = "ISC"
 [dependencies]
 embedded-hal = "1.0.0"
 embedded-hal-async = { version = "1.0.0", optional =  true }
-riscv = { path = "../riscv", version = "0.11.1" }
+riscv = { path = "../riscv", version = "0.12.0" }
 riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
 
 [dev-dependencies]

riscv-peripheral/src/aclint.rs

@@ -87,7 +87,7 @@ pub(crate) mod test {
                 Err(Error::InvalidVariant(number as usize))
             } else {
                 // SAFETY: valid context number
-                Ok(unsafe { core::mem::transmute(number) })
+                Ok(unsafe { core::mem::transmute::<u16, HartId>(number) })
             }
         }
     }

riscv-rt/CHANGELOG.md

@@ -9,19 +9,21 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- Add `no-exceptions` feature to opt-out the default implementation of `_dispatch_exception`
+- Add `no-interrupts` feature to opt-out the default implementation of `_dispatch_core_interrupt`
 - Add `pre_init_trap` to detect early errors during the boot process.
 - Add `v-trap` feature to enable interrupt handling in vectored mode.
 - Add `interrupt` proc macro to help defining interrupt handlers.
-If `v-trap` feature is enabled, this macro also generates its corresponding trap.
+  If `v-trap` feature is enabled, this macro also generates its corresponding trap.
 
 ### Changed
 
 - Moved all the assembly code to `asm.rs`
 - Use `weak` symbols for functions such as `_mp_hook` or `_start_trap`
 - `abort` is now `weak`, so it is possible to link third-party libraries including this symbol.
 - Made `cfg` variable selection more robust for custom targets
-- `_start_trap_rust` now only deals with exceptions. When an interrupt is detected, it now calls
-to `_dispatch_interrupt`.
+- `_start_trap_rust` now relies on `_dispatch_exception` and `_dispatch_core_interrupt`.
+  This change allows more flexibility for targets with non-standard exceptions and interrupts.
 - Upgrade rust-version to 1.61
 - Update `syn` to version 2.0
 

riscv-rt/Cargo.toml

@@ -13,7 +13,7 @@ edition = "2021"
 links = "riscv-rt" # Prevent multiple versions of riscv-rt being linked
 
 [dependencies]
-riscv = {path = "../riscv", version = "0.11.1"}
+riscv = { path = "../riscv", version = "0.12.0" }
 riscv-rt-macros = { path = "macros", version = "0.2.1" }
 
 [dev-dependencies]
@@ -23,3 +23,5 @@ panic-halt = "0.2.0"
 s-mode = ["riscv-rt-macros/s-mode"]
 single-hart = []
 v-trap = ["riscv-rt-macros/v-trap"]
+no-interrupts = []
+no-exceptions = []

riscv-rt/macros/Cargo.toml

@@ -11,6 +11,7 @@ license = "MIT OR Apache-2.0"
 name = "riscv-rt-macros"
 repository = "https://github.com/rust-embedded/riscv"
 version = "0.2.1"
+edition = "2021"
 
 [lib]
 proc-macro = true

riscv-rt/src/asm.rs

@@ -287,38 +287,6 @@ riscv_rt_macros::vectored_interrupt_trap_riscv32!();
 #[cfg(all(riscv64, feature = "v-trap"))]
 riscv_rt_macros::vectored_interrupt_trap_riscv64!();
 
-#[cfg(feature = "v-trap")]
-cfg_global_asm!(
-    // Set the vector mode to vectored.
-    r#".section .trap, "ax"
-    .weak _vector_table
-    .type _vector_table, @function
-    
-    .option push
-    .balign 0x4 // TODO check if this is the correct alignment
-    .option norelax
-    .option norvc
-    
-    _vector_table:
-        j _start_trap                     // Interrupt 0 is used for exceptions
-        j _start_SupervisorSoft_trap
-        j _start_DefaultHandler_trap      // Interrupt 2 is reserved
-        j _start_MachineSoft_trap
-        j _start_DefaultHandler_trap      // Interrupt 4 is reserved
-        j _start_SupervisorTimer_trap
-        j _start_DefaultHandler_trap      // Interrupt 6 is reserved
-        j _start_MachineTimer_trap
-        j _start_DefaultHandler_trap      // Interrupt 8 is reserved
-        j _start_SupervisorExternal_trap
-        j _start_DefaultHandler_trap      // Interrupt 10 is reserved
-        j _start_MachineExternal_trap
-
-        // default table does not include the remaining interrupts.
-        // Targets with extra interrupts should override this table.
-    
-    .option pop"#,
-);
-
 #[rustfmt::skip]
 global_asm!(
     ".section .text.abort

riscv-rt/src/exceptions.rs

@@ -0,0 +1,53 @@
+use crate::TrapFrame;
+
+extern "C" {
+    fn InstructionMisaligned(trap_frame: &TrapFrame);
+    fn InstructionFault(trap_frame: &TrapFrame);
+    fn IllegalInstruction(trap_frame: &TrapFrame);
+    fn Breakpoint(trap_frame: &TrapFrame);
+    fn LoadMisaligned(trap_frame: &TrapFrame);
+    fn LoadFault(trap_frame: &TrapFrame);
+    fn StoreMisaligned(trap_frame: &TrapFrame);
+    fn StoreFault(trap_frame: &TrapFrame);
+    fn UserEnvCall(trap_frame: &TrapFrame);
+    fn SupervisorEnvCall(trap_frame: &TrapFrame);
+    fn MachineEnvCall(trap_frame: &TrapFrame);
+    fn InstructionPageFault(trap_frame: &TrapFrame);
+    fn LoadPageFault(trap_frame: &TrapFrame);
+    fn StorePageFault(trap_frame: &TrapFrame);
+    fn ExceptionHandler(trap_frame: &TrapFrame);
+}
+
+#[doc(hidden)]
+#[no_mangle]
+pub static __EXCEPTIONS: [Option<unsafe extern "C" fn(&TrapFrame)>; 16] = [
+    Some(InstructionMisaligned),
+    Some(InstructionFault),
+    Some(IllegalInstruction),
+    Some(Breakpoint),
+    Some(LoadMisaligned),
+    Some(LoadFault),
+    Some(StoreMisaligned),
+    Some(StoreFault),
+    Some(UserEnvCall),
+    Some(SupervisorEnvCall),
+    None,
+    Some(MachineEnvCall),
+    Some(InstructionPageFault),
+    Some(LoadPageFault),
+    None,
+    Some(StorePageFault),
+];
+
+#[export_name = "_dispatch_exception"]
+#[inline]
+unsafe extern "C" fn dispatch_exception(trap_frame: &TrapFrame, code: usize) {
+    if code < __EXCEPTIONS.len() {
+        match &__EXCEPTIONS[code] {
+            Some(handler) => handler(trap_frame),
+            None => ExceptionHandler(trap_frame),
+        }
+    } else {
+        ExceptionHandler(trap_frame);
+    }
+}