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ucause only as readable bits
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src/register/ucause.rs

Lines changed: 0 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,5 @@
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//! ucause register
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pub use crate::register::mcause::{Interrupt, Exception, Trap};
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/// ucause register
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#[derive(Clone, Copy, Debug)]
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pub struct Ucause {
@@ -14,47 +12,6 @@ impl Ucause {
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pub fn bits(&self) -> usize {
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self.bits
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}
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/// Returns the code field
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pub fn code(&self) -> usize {
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match () {
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#[cfg(target_pointer_width = "32")]
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() => self.bits & !(1 << 31),
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#[cfg(target_pointer_width = "64")]
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() => self.bits & !(1 << 63),
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#[cfg(target_pointer_width = "128")]
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() => self.bits & !(1 << 127),
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}
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}
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/// Trap Cause
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#[inline]
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pub fn cause(&self) -> Trap {
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if self.is_interrupt() {
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Trap::Interrupt(Interrupt::from(self.code()))
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} else {
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Trap::Exception(Exception::from(self.code()))
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}
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}
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/// Is trap cause an interrupt.
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#[inline]
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pub fn is_interrupt(&self) -> bool {
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match () {
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#[cfg(target_pointer_width = "32")]
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() => self.bits & (1 << 31) == 1 << 31,
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#[cfg(target_pointer_width = "64")]
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() => self.bits & (1 << 63) == 1 << 63,
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#[cfg(target_pointer_width = "128")]
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() => self.bits & (1 << 127) == 1 << 127,
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}
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}
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/// Is trap cause an exception.
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#[inline]
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pub fn is_exception(&self) -> bool {
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!self.is_interrupt()
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}
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}
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read_csr_as!(Ucause, 0x042, __read_ucause);

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