Merge #12 #14

12: Add some S-Mode CSRs r=dvc94ch a=wangrunji0408

Add these S-Mode CSRs:
- `sstatus`
- `stvec`
- `sie`
- `sip`
- `scause`
- `stval`
- `sscratch`
- `sepc`
- `satp`

as well as:
- `time`
- `timeh`

and S-Mode instructions:
- `sfence.vma`

Most of the code have been tested in the [RustOS](https://github.com/wangrunji0408/RustOS) project.

14: Remove ecall and *ret instructions from riscv::asm r=dvc94ch a=Disasm

* *ret instructions should not be used directly in Rust code, they should be used in handlers, written in asm ([example](https://github.com/rust-embedded/riscv-rt/blob/273f0d4f70418a7602678632dcc78dbe24208fe2/src/lib.rs#L294-L340)).
* ecall instruction should be wrapped into something like syscall(), which should be declared in another platform-specific crate.

Co-authored-by: WangRunji <[email protected]>
Co-authored-by: Vadim Kaushan <[email protected]>

Author: 3 people

Cargo.toml

@@ -10,6 +10,7 @@ license = "ISC"
 
 [dependencies]
 bare-metal = "0.2.0"
+bit_field = "0.9.0"
 
 [features]
 inline-asm = []

src/asm.rs

@@ -16,9 +16,17 @@ macro_rules! instruction {
 
 
 /// Priviledged ISA Instructions
-instruction!(ecall, "ecall");
 instruction!(ebreak, "ebreak");
-instruction!(uret, "uret");
-instruction!(sret, "sret");
-instruction!(mret, "mret");
 instruction!(wfi, "wfi");
+instruction!(sfence_vma_all, "sfence.vma");
+
+
+#[inline]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+pub unsafe fn sfence_vma(asid: usize, addr: usize) {
+    asm!("sfence.vma $0, $1" :: "r"(asid), "r"(addr) :: "volatile");
+}
+
+#[inline]
+#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+pub fn sfence_vma(_asid: usize, _addr: usize) {}

src/lib.rs

@@ -12,6 +12,7 @@
 #![feature(const_fn)]
 
 extern crate bare_metal;
+extern crate bit_field;
 
 pub mod asm;
 pub mod interrupt;

src/register/macros.rs

@@ -0,0 +1,129 @@
+macro_rules! read_csr {
+    ($csr_number:expr) => {
+        /// Reads the CSR
+        #[inline]
+        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        unsafe fn _read() -> usize {
+            let r: usize;
+            asm!("csrrs $0, $1, x0" : "=r"(r) : "i"($csr_number) :: "volatile");
+            r
+        }
+
+        #[inline]
+        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+        unsafe fn _read() -> usize {
+            unimplemented!()
+        }
+    };
+}
+
+macro_rules! read_csr_as {
+    ($register:ident, $csr_number:expr) => {
+        read_csr!($csr_number);
+
+        /// Reads the CSR
+        #[inline]
+        pub fn read() -> $register {
+            $register { bits: unsafe{ _read() } }
+        }
+    };
+}
+macro_rules! read_csr_as_usize {
+    ($csr_number:expr) => {
+        read_csr!($csr_number);
+
+        /// Reads the CSR
+        #[inline]
+        pub fn read() -> usize {
+            unsafe{ _read() }
+        }
+    };
+}
+
+macro_rules! write_csr {
+    ($csr_number:expr) => {
+        /// Writes the CSR
+        #[inline]
+        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        unsafe fn _write(bits: usize) {
+            asm!("csrrw x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile");
+        }
+
+        #[inline]
+        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+        unsafe fn _write(_bits: usize) {
+            unimplemented!()
+        }
+    };
+}
+
+macro_rules! write_csr_as_usize {
+    ($csr_number:expr) => {
+        write_csr!($csr_number);
+
+        /// Writes the CSR
+        #[inline]
+        pub fn write(bits: usize) {
+            unsafe{ _write(bits) }
+        }
+    };
+}
+
+macro_rules! set {
+    ($csr_number:expr) => {
+        /// Set the CSR
+        #[inline]
+        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        unsafe fn _set(bits: usize) {
+            asm!("csrrs x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile");
+        }
+
+        #[inline]
+        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+        unsafe fn _set(_bits: usize) {
+            unimplemented!()
+        }
+    };
+}
+
+macro_rules! clear {
+    ($csr_number:expr) => {
+        /// Clear the CSR
+        #[inline]
+        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        unsafe fn _clear(bits: usize) {
+            asm!("csrrc x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile");
+        }
+
+        #[inline]
+        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+        unsafe fn _clear(_bits: usize) {
+            unimplemented!()
+        }
+    };
+}
+
+macro_rules! set_csr {
+    ($set_field:ident, $e:expr) => {
+        #[inline]
+        pub unsafe fn $set_field() {
+            _set($e);
+        }
+    }
+}
+
+macro_rules! clear_csr {
+    ($clear_field:ident, $e:expr) => {
+        #[inline]
+        pub unsafe fn $clear_field() {
+            _clear($e);
+        }
+    }
+}
+
+macro_rules! set_clear_csr {
+    ($set_field:ident, $clear_field:ident, $e:expr) => {
+        set_csr!($set_field, $e);
+        clear_csr!($clear_field, $e);
+    }
+}

src/register/mod.rs

@@ -10,6 +10,9 @@
 //! - minstreth
 //! - mhpmcounter[3-31]h
 
+#[macro_use]
+mod macros;
+
 pub mod mcause;
 pub mod mcycle;
 pub mod mcycleh;
@@ -22,3 +25,16 @@ pub mod misa;
 pub mod mstatus;
 pub mod mtvec;
 pub mod mvendorid;
+
+pub mod sstatus;
+pub mod stvec;
+pub mod sie;
+pub mod sip;
+pub mod scause;
+pub mod stval;
+pub mod satp;
+pub mod sscratch;
+pub mod sepc;
+
+pub mod time;
+pub mod timeh;

src/register/satp.rs

@@ -0,0 +1,108 @@
+//! satp register
+
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+use bit_field::BitField;
+
+/// satp register
+#[derive(Clone, Copy, Debug)]
+pub struct Satp {
+    bits: usize,
+}
+
+impl Satp {
+    /// Returns the contents of the register as raw bits
+    #[inline]
+    pub fn bits(&self) -> usize {
+        self.bits
+    }
+
+    /// Current address-translation scheme
+    #[inline]
+    #[cfg(target_arch = "riscv32")]
+    pub fn mode(&self) -> Mode {
+        match self.bits.get_bit(31) {
+            false => Mode::Bare,
+            true => Mode::Sv32,
+        }
+    }
+
+    /// Current address-translation scheme
+    #[inline]
+    #[cfg(target_arch = "riscv64")]
+    pub fn mode(&self) -> Mode {
+        match self.bits.get_bits(60..64) {
+            0 => Mode::Bare,
+            8 => Mode::Sv39,
+            9 => Mode::Sv48,
+            10 => Mode::Sv57,
+            11 => Mode::Sv64,
+            _ => unreachable!(),
+        }
+    }
+
+    /// Address space identifier
+    #[inline]
+    #[cfg(target_arch = "riscv32")]
+    pub fn asid(&self) -> usize {
+        self.bits.get_bits(22..31)
+    }
+
+    /// Address space identifier
+    #[inline]
+    #[cfg(target_arch = "riscv64")]
+    pub fn asid(&self) -> usize {
+        self.bits.get_bits(44..60)
+    }
+
+    /// Physical page number
+    #[inline]
+    #[cfg(target_arch = "riscv32")]
+    pub fn ppn(&self) -> usize {
+        self.bits.get_bits(0..22)
+    }
+
+    /// Physical page number
+    #[inline]
+    #[cfg(target_arch = "riscv64")]
+    pub fn ppn(&self) -> usize {
+        self.bits.get_bits(0..44)
+    }
+}
+
+#[cfg(target_arch = "riscv32")]
+pub enum Mode {
+    Bare = 0,
+    Sv32 = 1,
+}
+
+#[cfg(target_arch = "riscv64")]
+pub enum Mode {
+    Bare = 0,
+    Sv39 = 8,
+    Sv48 = 9,
+    Sv57 = 10,
+    Sv64 = 11,
+}
+
+read_csr_as!(Satp, 0x180);
+write_csr!(0x180);
+
+#[inline]
+#[cfg(target_arch = "riscv32")]
+pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) {
+    let mut bits = 0usize;
+    bits.set_bits(31..32, mode as usize);
+    bits.set_bits(22..31, asid);
+    bits.set_bits(0..22, ppn);
+    _write(bits);
+}
+
+#[inline]
+#[cfg(target_arch = "riscv64")]
+pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) {
+    let mut bits = 0usize;
+    bits.set_bits(60..64, mode as usize);
+    bits.set_bits(44..60, asid);
+    bits.set_bits(0..44, ppn);
+    _write(bits);
+}